Combination Gates: Understanding NAND & NOR in Physics

[Richie Smash]

Hello, I'm currently studying physics at the CSEC level in the caribbean, or what would be equivalent to the GCSE level in England I believe, and I've arrived at Logic Gates.

I've gone through the various gates they ask for at this level such as: AND, OR, NAND, NOT and NOR gates.

I believe I understand each of these gates' specific functions, but then the next topic is about combination gates.

My textbook states, ''The use of several or more types of gates together to perform given functions is known as combinational logic.''

They then say NAND and NOR gates are most commonly used in making these combinational gates, and proceed to show diagrams of various NAND and NOR gates connected together, and their respective truth tables, but these diagrams are really confusing me. I don't seem to have a grasp on this topic.
http://uploads.im/MuU7e.jpg
http://uploads.im/YQpDU.jpg

Here are the two images, (I know off site sources are discouraged but I don't know how to attach an image here)

As you can see from these, they have various NAND and NOR together to produce say NOT, AND and OR gates, I just don't see how the truth tables add up, I just don't know what's going on here, does anyone know in detail about this subject?

 

[anorlunda]

The diagrams would help. Use the UPLOAD button to the right of POST REPLY and PREVIEW.

 

[DavidSnider]

Maybe it will help to think of the logic gates like functions:

NAND(x,y) = IF X AND Y THEN 0 ELSE 1
NOT(x) = NAND(x,x)
AND(x,y) = NOT(NAND(x,y))
OR(x,y) = NAND(NOT(x),NOT(y))
etc, etc,

 

[Drakkith]

As you can see from these, they have various NAND and NOR together to produce say NOT, AND and OR gates, I just don't see how the truth tables add up, I just don't know what's going on here, does anyone know in detail about this subject?

Take a look at the OR gate in the 2nd diagram. This OR gate is actually composed of 3 NAND gates. If you start at the 1st row on the truth table, you'll see that the A and B inputs are 0, so the leftmost NAND gates output 1's. These 1's are then input into the third NAND gate, which outputs a 0.

For the next row, A is 0, so the top gate outputs a 1, and B is 1, so the bottom gate outputs a zero. C is the output of the top gate and is 1 and D is the output of the bottom gate and is 0. Thus the last NAND gate outputs a 1.

The next two rows follow the same principle. Remember that A and B are the inputs to the OR gate. C and D are not. Their values in the truth table depend on A and B.

Does that make sense?

 

[Delta2]

Perhaps what confuses you is how the output of a gate serves as an input for another gate. The final result that is shown in the truth table, is not these intermediate outputs/inputs but the final output of the final gate.

 

[Drakkith]

Perhaps what confuses you is how the output of a gate serves as an input for another gate. The final result that is shown in the truth table, is not these intermediate outputs/inputs but the final output of the final gate.

Unless I'm mistaken, those intermediate connections appear to be in the truth tables linked by the OP.

 

[Delta2]

Unless I'm mistaken, those intermediate connections appear to be in the truth tables linked by the OP.

Ah you are absolutely right, I myself was looking only at the final column...

 

[jim hardy]

Yes. Just grunt through them one at a time working left to right.

At first it's quite foreign to our brain. As with any new language it's "Practice, Practice, Practice".
It helps me to talk through them. Hearing is wired into our brain via a different pathway than reading and it helps to get more of the 'little gray cells' involved.

old jim

 

[sophiecentaur]

Yes. Just grunt through them one at a time working left to right.

At first it's quite foreign to our brain. As with any new language it's "Practice, Practice, Practice".
It helps me to talk through them. Hearing is wired into our brain via a different pathway than reading and it helps to get more of the 'little gray cells' involved.

old jim

Let's hear it for hearing! I often struggle to remember a name or equation but, once I hear someone else actually say it, it goes in and stays there (or at least, stays for as long as an ageing brain can retain anything, post 2101). I'm also very aware of the pathways you refer to during the 'recall' process.

 

[Richie Smash]

Maybe it will help to think of the logic gates like functions:

NAND(x,y) = IF X AND Y THEN 0 ELSE 1
NOT(x) = NAND(x,x)
AND(x,y) = NOT(NAND(x,y))
OR(x,y) = NAND(NOT(x),NOT(y))
etc, etc,

Take a look at the OR gate in the 2nd diagram. This OR gate is actually composed of 3 NAND gates. If you start at the 1st row on the truth table, you'll see that the A and B inputs are 0, so the leftmost NAND gates output 1's. These 1's are then input into the third NAND gate, which outputs a 0.

For the next row, A is 0, so the top gate outputs a 1, and B is 1, so the bottom gate outputs a zero. C is the output of the top gate and is 1 and D is the output of the bottom gate and is 0. Thus the last NAND gate outputs a 1.

The next two rows follow the same principle. Remember that A and B are the inputs to the OR gate. C and D are not. Their values in the truth table depend on A and B.

Does that make sense?

Perhaps what confuses you is how the output of a gate serves as an input for another gate. The final result that is shown in the truth table, is not these intermediate outputs/inputs but the final output of the final gate.

Hi to all of you, Next time I will upload the pictures, I found the button but It seems to be giving me an error message.

To start things off,I appreciate that method you have there David Snider, as functions, but I'm still a bit fuzzy about that way.

To Drakkith, your explanation actually did clear things up for me. When looking at that second OR gate which consists of 3 NAND gates, I see how the inputs for each gate will give you the same output for an OR gate, as you say, A and B are 0's so they will input as two 1's on the left side, and when going through the final NAND gate the two 1's will now be a 0 again. Just like an OR gate two 0's make another 0, I think I have a better understanding now that really did make sense.

To Delta, I think that is exactly what was confusing me, still is slightly but Drakkith's explanation did offer me some insight. The NOT gate consisting of 1 NAND gate on the second link still is a bit confusing however.

Thanks to all of your for replying.

 

[donpacino]

The NOT gate consisting of 1 NAND gate on the second link still is a bit confusing however.

Work out the truth table for yourself!

 

[Richie Smash]

Work out the truth table for yourself!

Ah, I found out why it was confusing, because at first I thought it just said A, and there was no number on the diagram. But the answer lies within the truth table, it simply means if A is 0 output will be 1 etc.
Another thing that confused me is that there seemed to be a junction joining those two wires, I'm quite a novice here and currently self taught with the help of friends.

But i now understand that it means once there is a junction joining the two, the output will either be two 1's or two 0's never a 1 and a 0 or vice versa.

 

[donpacino]

Another thing that confused me is that there seemed to be a junction joining those two wires, I'm quite a novice here and currently self taught with the help of friends.

That's fine. These gates are the building blocks for all things digital. Learn to love them. Once you get good at learning this kind of stuff it will get easier!