Constructing a CMOS AND circuit with MOSFETs

• Engineering

Homework Statement:

Construct a basic CMOS circuit AND function with 2 inputs.

Relevant Equations:

-
Hi all :)
So I constructed this based on a video tutorial, p, and n MOS, and was wondering if it was correct before I combine them. Also, it looks very different from what the proposed answer is.

Since the equation is z=ab,

The pull-down diagram looks like this:

and the pull-up is z= a'+b'

Combining my diagrams, I don't feel like I can achieve the outcome as shown above.

Is there a problem with my diagrams?

Cheers

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Baluncore
2019 Award
Do you notice the two transistors on the RHS of the proposed solution?
What do they do?

Do you notice the two transistors on the RHS of the proposed solution?
What do they do?
Is it an inverter? I'm pretty new at that.

Baluncore
2019 Award
It is an inverting buffer.
What implications does that have to the intermediate signal at the input to the buffer.

It will 'invert' the input, which means 1 becomes a 0 and 0 becomes a 1.

As expected, or what you have stated, my expected outcome has no inverting buffer at the right side. Do I need to include one in?
I'm using:

as an example for the video tutorial and he doesn't mention this anywhere.

Ok I realised his inputs are like separated (so there's 2 a's inputs instead of one)

Baluncore
2019 Award
You should have a buffer to provide some voltage gain in the gate.
Simple two transistor CMOS buffers are inverting buffers.
If you need a non-inverting buffer you must use two inverting buffers.

Parallel PMOS at the top will pull up if either input is low.
Series NMOS at the bottom will pull down only when both inputs are high.
I think you have designed a simple NAND gate without a buffer.

A NAND gate can be an AND gate followed by an inverting buffer.
An AND gate can be a NAND gate followed by an inverting buffer.

Joshy
Gold Member
Do you feel comfortable with how a PMOS or NMOS work alone? I know from your other thread you're in an introductory course.

Something that really helped me work with these during my first run of IC design for digital circuits was to think of these as switches... is it on or off? Here's a NMOS example.

The gate is the thing that controls whether or not the switch is open or closed. If the gate is high, then it closes the switch connecting the source and the drain; if the gate is low, then the switch is open and the two wires stay separated (not touching). If you like the water analogy then you can think of the gate as the valve that allows you to control whether or not water is flowing through the pipes.

The PMOS is also controlled by the gate, but its behaviour does the opposite. If the gate is high, then it opens the switch; otherwise: it closes it. Lets try to the switch idea on the inverter.

On the left side going from left to right when the input (gate) is high, then the PMOS on top is open and the NMOS on the bottom is closed. The output is connected to the one that is low, and so the derived output is low. The one on the right when the input is low now the NMOS is closed, but the PMOS opens up and the high is connected to the output.

I know i'm overly simplifying it, but I also know you're in an introductory module and you're still trying to get by with the Boolean logic. Hopefully this might help?

Did your book show you the example of a NAND? Others are already pulling you towards it thinking about a NAND (not and) and inverting it with an inverter (not). Do the circuits on the left side look suspiciously familiar to something? How about the last two on the right?

Tom.G
Do you feel comfortable with how a PMOS or NMOS work alone? I know from your other thread you're in an introductory course.

Something that really helped me work with these during my first run of IC design for digital circuits was to think of these as switches... is it on or off? Here's a NMOS example.

View attachment 260726

The gate is the thing that controls whether or not the switch is open or closed. If the gate is high, then it closes the switch connecting the source and the drain; if the gate is low, then the switch is open and the two wires stay separated (not touching). If you like the water analogy then you can think of the gate as the valve that allows you to control whether or not water is flowing through the pipes.

The PMOS is also controlled by the gate, but its behaviour does the opposite. If the gate is high, then it opens the switch; otherwise: it closes it. Lets try to the switch idea on the inverter.

View attachment 260727

On the left side going from left to right when the input (gate) is high, then the PMOS on top is open and the NMOS on the bottom is closed. The output is connected to the one that is low, and so the derived output is low. The one on the right when the input is low now the NMOS is closed, but the PMOS opens up and the high is connected to the output.

I know i'm overly simplifying it, but I also know you're in an introductory module and you're still trying to get by with the Boolean logic. Hopefully this might help?

Did your book show you the example of a NAND? Others are already pulling you towards it thinking about a NAND (not and) and inverting it with an inverter (not). Do the circuits on the left side look suspiciously familiar to something? How about the last two on the right?

Hi there.
Yea, I do understand the concept of using 'switches' to determine whether the output is high or low given a circuit, so that's okay for me. I'm just curious why when combining the two inputs of A together, why will I need to add an inverter before the output? Cheers

Joshy
Gold Member
The very top diagram in the original post is very hard to follow. Here's what I'm interpreting from the post.

It looks like you have the two inputs, but some of the terminals are floating or missing; the output is connected to ground so it's always low.

Since you're familiar with this whole switch idea what I recommend is trying the truth table on the circuit without the inverter behind it. Just go through it one row at a time let us know what you get :)

$$\begin{array}{|c|c|c|} \hline A & B & OUT\\ \hline 0 & 0 & \\ \hline 0 & 1 & \\ \hline 1 & 0 & \\ \hline 1 & 1 & \\ \hline \end{array}$$

Tom.G