Decoder and register in Verilog

  • Thread starter ACLerok
  • Start date
  • Tags
    Decoder
In summary, the conversation discusses the development of a decoder to enable the writing of data to a single register in a register file with 16 instances. The proposed method involves creating a decoder module to receive a 4-bit hexadecimal number and output a 16-bit binary number, where the digit place with a value of 1 corresponds to the register to be written. This method is similar to a demultiplexor. The conversation ends with a request for clarification on the purpose of the "received register number."
  • #1
ACLerok
194
0
I'm trying to program the write action for a register file.
Basically I have 16 instances of a register file whose inputs are:

enbl - the enable signal
write_data - data to be written to register
clk - clock

and a single output, out, which is the value of the register.

The problem I'm having is developing a decoder that will set the enbl signal of only a single register to 1 for writing to the register so only 1 register will be written at any given time. All 16 registers will be of the same register module. I am thinking of creating a decoder module that receives the number of the register to be written, and then outputs a 16-bit binary number (called enbl_sig) that will be all 0's except for a single 1 in which the digit place corresponds to the register number to be written. Therefore I can just send enbl[0], enbl[1]... etc to each register instance. The register instance with enbl[.]=1 will be the one that will write the data to the register. Also, the received register number to write to will be received is a 4-bit hexadecimal number.

Sorry if this sounds confusing, but I don't know how else I would be able to do it. Does anyone have any suggestions or perhaps an easier method to accomplish this? I don't need the exact code, just the method of taking a 4-bit hexadecimal number and then outputting the desired 16-bit binary number. Thanks again.
 
Technology news on Phys.org
  • #2
ACLerok said:
The problem I'm having is developing a decoder that will set the enbl signal of only a single register to 1 for writing to the register so only 1 register will be written at any given time. All 16 registers will be of the same register module. I am thinking of creating a decoder module that receives the number of the register to be written, and then outputs a 16-bit binary number (called enbl_sig) that will be all 0's except for a single 1 in which the digit place corresponds to the register number to be written. Therefore I can just send enbl[0], enbl[1]... etc to each register instance. The register instance with enbl[.]=1 will be the one that will write the data to the register. Also, the received register number to write to will be received is a 4-bit hexadecimal number.

It looks to me that what you are attempting to build is actually a demultiplexor.

I was following what you said until

The register instance with enbl[.]=1 will be the one that will write the data to the register. Also, the received register number to write to will be received is a 4-bit hexadecimal number.

I am having the most trouble here in terms of understanding what you want to do. Can you clarify a little bit regarding your "Received Register Number"?
 
  • #3


To program the write action for a register file in Verilog, you will need to use a decoder and a register module. The decoder will be responsible for selecting which register will be written to, while the register module will actually perform the write operation.

First, let's look at the decoder module. As you mentioned, it will receive a 4-bit hexadecimal number representing the register to be written to. The decoder will then output a 16-bit binary number, where only one bit will be set to 1. This bit will correspond to the register to be written to.

To achieve this, you can use a case statement in your decoder module. The case statement will take in the 4-bit hexadecimal number and based on its value, set the corresponding bit in the 16-bit output. For example, if the input is "0000" (register 0), the output will be "0000000000000001" with the first bit set to 1. This will ensure that only one register will have its enbl signal set to 1 at any given time.

Next, in your register module, you will need to use the enbl signal as a control signal. This means that the write operation will only be performed when the enbl signal is set to 1. You can use an "if" statement in your register module to check if the enbl signal is set to 1 and if so, perform the write operation using the write_data input.

Finally, in your top-level module, you can instantiate 16 instances of the register module and connect them to the decoder module. Each instance will have its own enbl signal, which will be controlled by the decoder output. This way, only one register will be written to at a time.

In summary, to program the write action for a register file in Verilog, you will need to use a decoder module to select which register will be written to, and a register module to actually perform the write operation. Use a case statement in the decoder module to set the enbl signal for the selected register, and use this enbl signal as a control signal in your register module. Instantiate 16 instances of the register module in your top-level module and connect them to the decoder output to control the write operation.
 

1. What is a decoder in Verilog?

A decoder in Verilog is a combinational logic circuit that converts a binary input signal into multiple output signals depending on the input value. It essentially decodes the input signal to select a specific output signal.

2. How is a decoder implemented in Verilog?

A decoder can be implemented in Verilog using the "case" statement or the "if-else" statement. Both of these statements allow for conditional logic based on the input value to determine the output signals.

3. What is the purpose of a register in Verilog?

A register in Verilog is a sequential logic circuit that stores a single binary value. It is commonly used to store data between clock cycles and is essential for creating sequential circuits such as counters and shift registers.

4. How do you declare a register in Verilog?

To declare a register in Verilog, you need to use the "reg" keyword followed by the desired name and size of the register. For example, "reg [7:0] my_register" would declare an 8-bit register named "my_register".

5. What is the difference between a decoder and a register in Verilog?

A decoder is a combinational logic circuit that converts an input signal into multiple output signals, while a register is a sequential logic circuit that stores a single binary value. A decoder is used for selecting an output based on an input, while a register is used for storing data between clock cycles.

Similar threads

  • Programming and Computer Science
Replies
3
Views
1K
  • Electrical Engineering
Replies
12
Views
1K
  • Programming and Computer Science
Replies
30
Views
4K
  • Sticky
  • Programming and Computer Science
Replies
13
Views
4K
  • Engineering and Comp Sci Homework Help
Replies
10
Views
1K
  • Engineering and Comp Sci Homework Help
Replies
1
Views
1K
  • Programming and Computer Science
Replies
7
Views
3K
  • Programming and Computer Science
Replies
0
Views
416
  • Programming and Computer Science
Replies
3
Views
929
  • Engineering and Comp Sci Homework Help
Replies
5
Views
1K
Back
Top