Hey guys, I have two questions about something I'm trying to minimize. I'm making a binary to seven segment decoder in Verilog, and I have a truth table set up. The board I'm going to be placing this on is active low. My questions: I want to reduce, or minimize, this truth table, I was going to do it by each segment. So my inputs b0, b1, b2, b3 would be put on a k-map with respect to each segment. - Since my device is active low, does that change how I fill out my k-maps? I don't think so, but I haven't done any digital logic design in quite a while. Do I draw my boxes in terms of '0's instead of '1's since the '0's drive my logic? I.e. do I fill out the k-maps backwards? - When minimized, I will have seven reduced equations. One for each segment. I guess I just don't see the benefit of reducing the equations. Or how it works, even. I'm going to be implementing this in Verilog, so simply hard coding the inputs to a certain output directly off the truth table is pretty easy. What will having seven reduced equations for each segment actually do for me? Thanks!