Minimization with a binary to seven segment decoder in Verilog

[Maxwell]

Today I someone told me that if you map the 0's, you need to put them in product of sum form, not sum of products.

My VHDL code is attached.

I will go over your work, berkeman, and compare it to mine.

In the mean time, I coded the decoder with another method, and it works. So from now on this topic is purely for the purposes of knowing why the code was not working. I.e., there is no rush.

Thanks for the help so far.

 

[berkeman]

Today I someone told me that if you map the 0's, you need to put them in product of sum form, not sum of products.

Yeah, that's what I meant by inverting the equations for the 0's. When you invert a sum of products, you get a product of sums. Sorry if I wasn't clear about that.

The VHDL code is for the map of the 1's? or the 0's? If it's for the 0's, then it would need to have the equations inverted. Maybe just do the K-maps again, mapping the 1's (where the segments are off), and compare to my answers...

 

[Maxwell]

Ah, I see what you were saying now. I'm going to try that tonight.

The VHDL code is for mapped '0's - before I knew I needed a product of sums. I'll redo them tonight and see how it goes.

 

[ranger]

I did some sketching for the 4-bit binary to 7-segment display problem, and have attached some of the work. I haven't checked it in detail, but hopefully it will help. The truth table shows 0's where the segments are turned on, and I K-mapped the 1's for the final equations.

I'll check this against your work (and VHDL code when you post that), when I get a bit more time. Hope this helps.EDIT -- Hmmm. Guess I should have scanned them in color; that would have been more readable. Anyway, it should give you something to check against.

Why did you label your 7-seg like that? Isn't it suppose to be like http://www.engr.colostate.edu/~dga/mechatronics/figures/6-34.gif ?

 

[ranger]

Well I did some k-maps for segment B and came up with the following verilog code. I can't unload my work because the scanner broke. But its quite easy to reconstruct the gates from the code. My work is similar to berkeman's; I only relabeled the 7-segment display.

 module binaryToBSegSim;
    wire      bSeg,p1,p2; 
    reg       b0,b1,b2,b3;     
    
    and  g1(p1,~b1,b0,~b3);
    and  g2(p2,b1,~b0,~b3,b2);
    or   g3(bSeg,p1,p2); 
        
    initial       
        begin     
        
             $monitor 
             ($time,,,"b3 = %b b2 = %b b1 = %b b0 = %b, aSeg = %b",
                   b3,b2,b1,b0, bSeg);
              
             #10  b3 = 0; b2 = 0; b1 = 0; b0 = 0;
             #10  b3 = 0; b2 = 0; b1 = 0; b0 = 1;
             #10  b3 = 0; b2 = 0; b1 = 1; b0 = 0;
             #10  b3 = 0; b2 = 0; b1 = 1; b0 = 1;
             #10  b3 = 0; b2 = 1; b1 = 0; b0 = 0;
             #10  b3 = 0; b2 = 1; b1 = 0; b0 = 1;
             #10  b3 = 0; b2 = 1; b1 = 1; b0 = 0;
             #10  b3 = 0; b2 = 1; b1 = 1; b0 = 1;
             #10  b3 = 1; b2 = 0; b1 = 0; b0 = 0;
             #10  b3 = 1; b2 = 0; b1 = 0; b0 = 1;
              $finish;
        end     
endmodule

//--Here is the output:
/*
                  0  b3 = x b2 = x b1 = x b0 = x, aSeg = x
                  10  b3 = 0 b2 = 0 b1 = 0 b0 = 0, aSeg = 0
                  20  b3 = 0 b2 = 0 b1 = 0 b0 = 1, aSeg = 1
                  30  b3 = 0 b2 = 0 b1 = 1 b0 = 0, aSeg = 0
                  40  b3 = 0 b2 = 0 b1 = 1 b0 = 1, aSeg = 0
                  50  b3 = 0 b2 = 1 b1 = 0 b0 = 0, aSeg = 0
                  60  b3 = 0 b2 = 1 b1 = 0 b0 = 1, aSeg = 1
                  70  b3 = 0 b2 = 1 b1 = 1 b0 = 0, aSeg = 1
                  80  b3 = 0 b2 = 1 b1 = 1 b0 = 1, aSeg = 0
                  90  b3 = 1 b2 = 0 b1 = 0 b0 = 0, aSeg = 0

*/

 

[berkeman]

Why did you label your 7-seg like that? Isn't it suppose to be like http://www.engr.colostate.edu/~dga/mechatronics/figures/6-34.gif ?

Yikes, you might be right. I looked in my HP Opto catalog and just went from there, but I may have gone a bit too quickly. I'm at home now without the HP catalog, and a quick google gave me the same a-g ordering as you posted

http://www.ibiblio.org/kuphaldt/socratic/output/proj_ctr.pdf

Sorry if I confused anybody. I wish I could claim that I was just testing y'all again...but then again, if I were testing folks, you passed the test ranger!

 

[Maxwell]

Hey guys, sorry it took so long for me to reply. I've been finishing up some other work.

It turns out the problem was solved by using the product of sums instead of the sum of products for the active low device. The device works in simulation now, and I'll be testing it on a FPGA later.

Thank you both so much, berkeman and ranger! You were both very helpful and patient and I appreciate it very much.