How to Maintain Output Values in Verilog Like Registers?

[KingNothing]

Hi. I'm new to verilog and I'm trying to do something that to me, seems very simple. I have a file with some logic and outputs, and all I want is for the outputs to hold their values, like registers.

In other words, if output = 001, I want it to stay that way until it is re-assigned. The problem I am having, is that verilog won't let me assign my output or a wire to a register value.

Here is my code so far:

module coin_input(CI, button_out_signal, button_in);
	output [1:0] CI;
	output button_out_signal;
	input [3:0] button_in;
	
	wire [2:0] button_id;
	
	reg [1:0] CItemp;
	wire [1:0] CItemp2;
	assign CI[1] = CItemp2[1];
	assign CI[0] = CItemp2[0];
	assign CItemp2[1] = CItemp[1];
	assign CItemp2[0] = CItemp[0];
	
	
	//Connect buttons to button stabilizers
	//Button_Stabilizer(button_out, button1_in, enter)
	Button_Stabilizer	bs2(button_id[2], button_in[3], button_in[0]),
						bs1(button_id[1], button_in[2], button_in[0]),
						bs0(button_id[0], button_in[1], button_in[0]);
						
	//Convert button_id's to CI to give precedence to higher-value coins
	always @(posedge button_in[3]) begin
		{CItemp[1], CItemp[0]} <= 2'b11;
	end
	
	always @(posedge button_in[2]) begin
		{CItemp[1], CItemp[0]} <= 2'b10;
	end
	
	always @(posedge button_in[1]) begin
		{CItemp[1], CItemp[0]} <= 2'b01;
	end

	//Set button_out_signal to 1
	assign button_out_signal = button_in | 1'b0;
endmodule

You can see that I am using the register CItemp to hold the values that I want to store. I want to assign the output, CI, to this register value. How in the world do I do that?

 

[KingNothing]

I'm really very sorry, but I believe I have figured out what I was doing wrong above. I've traced it back to a different issue, actually.

The problem is that I have a circuit with three different inputs, and the circuit is supposed to react based on a positive edge from any of the inputs. For example, if input1 has a positive edge, the output should be set to 01. If input2 has a positive edge, the output should be set to 10.

I am having a serious issue coding this. I have one procedural statement to excute a bunch of code when there is a positive edge in either input:

always @(posedge button_id[2] or posedge button_id[1] or posedge button_id[0]) begin

But, I am not able to write good logic after that, because once inside that procedural statement, how can the code be aware of WHICH input generated a positive edge?