Design BCD 2-out-5 Encoder Using Logic Gates - 74210 Code

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The discussion focuses on designing a BCD 2-out-of-5 encoder using basic logic gates, specifically the 74210 code. Participants share their understanding of binary-coded decimal (BCD) and the requirements for the encoder, including truth tables and Karnaugh Maps (K-Maps) for simplifying logic expressions. Several users express challenges with K-Maps and circuit design in Micro Cap, seeking hints and feedback on their outputs. The conversation highlights the importance of verifying logic equations through testing and the potential to simplify designs further. Overall, the thread emphasizes collaborative problem-solving in digital logic design.
  • #31
MirrorM said:
So if you had a question on the number of IC's used, would the answer be 1 1/3 (three 3-input ANDs (one IC), and feed their outputs to a 3-input OR (1/3 IC)) or 2 IC's because is can't have 1/3 of an IC?( can you?)


Obviously, you'd have to round the number up to the next larger value, but remember, that you have several such equations (five in your problem), and the other equations might also need some 3-input ORs. Thus say that all of the equations needed eleven 3-input ANDs and four 3-input ORs. In that case your total IC requirement for 3-input ANDs would be four and for 3-input ORs would be two. You use the fractional figures to count the number of ICs needed for each equation, then when you've added up the total for all of your equations, round the number up.

Even better, count the gates of each type needed for each equation, then
add these up, divide the total gate count needed for each gate type, by the number per IC, and round up.

KM
 
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  • #32
Just for the exercise, I decided to try this problem, using the SPOS (Simple-Product-Of-Sums) approach) and this time, got nine/ten ICs. (Using the SSOP approach I also got, as I recall, ten ICs, counting inverters.) To go back over the process, what I did was the following, this time looking for the SPOS answer:

First I mapped each of the five desired output signals, but this time for the "zeros". (You should check it in case I made an error.) What I got was the following, in the case of P7:

P7' = A'B'C' + B'C'D + ABCD'

Then I combined terms to get:

P7' = (A' + D)B'C' + ABCD'

Then, DeMorgan was applied to get P7', to get what follows:

P7 = (AD' + B + C)(A' + B' + C' + D)

This 'term' requires:

2' 2-input AND
1, 3-input OR
1, 4-input OR

Doing the same for the other four terms got a total requirement for:

1 4 input OR = 1 IC
1 3 input OR = 1 IC
12 2 input OR = 3 IC
7 2 input AND = 2 IC
4 3 input AND = 2 IC
4 Inverter = 1 IC

Total = 10 IC

It can be noted here, though that both the 3-input OR and the 4-input OR functions can be handled by a single dual-4-input OR IC. (Where a 3-input OR is needed, one of the inputs can simply be grounded.) This would leave a requirement for nine ICs.

It might be worth something extra if you work the problem out this way in addition to the SSOP way.

KM
 

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