Solving Delays in 8:3 Encoder Design with Verilog

[polaris90]

I have a question about encoders. In one of my classes we had to design a 8 to 3 encoder using verilog. my code is the following.

module encoder( S, D, E);
input E;  //enable
input [7:0] D;  //input x, y, z
output[2:0] S;  //ouput
reg [2:0] S;
always @ (E or D)begin
	if (E==1) begin
	case (D)
	8'b00000001 : S = 3'b000;
	8'b00000010 : S = 3'b001;
	8'b00000100 : S = 3'b010;
	8'b00001000 : S = 3'b011;
	8'b00010000 : S = 3'b100;
	8'b00100000 : S = 3'b101;
	8'b01000000 : S = 3'b110;
	8'b10000000 : S = 3'b111;
	default :S =3'bx;
endcase
end
end
endmodule

I simulated my encoder using a functional simulation and the output is shown in the picture attached. I see that there are many delays in the output(shown my the glitches in the graph). My question, is why are these delays really produced. When looking at the logic circuit, every output corresponds to 8 inputs, in which one of them is a 1. I see it's a single step with only one gate delay unless I'm wrong. Then when looking at the priority encoder the delay seems to be higher. Could someone give me some feedback on this?

 

[the_emi_guy]

The simulator is identifying logic hazards.

For example at 20ns we have three events occurring simultaneously:
D[5] rising, D[6] falling, and D[7] falling.

The simulator is showing you that during this transition, the state: D[5] low, D[6] high, D[7] low may be reached, even if very briefly, causing S[0]=low.