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Yeah I just realized that, how about this?mfb said:I don't see how. Check your C_{out}, however. If b_{1} is zero, your carry is always on.
While that is a 2-bit adder it is designed with gates other than NAND. Granted I could simply replace each gate with the NAND equivalent, I kinda want to make this with the least amount of gates possible. Which is why I have come to this forum to see if I can get this simplified as much as possible.Svein said:
Are you familiar with Karnaugh diagrams? ( https://en.wikipedia.org/wiki/Karnaugh_map )Crushforce said:While that is a 2-bit adder it is designed with gates other than NAND. Granted I could simply replace each gate with the NAND equivalent, I kinda want to make this with the least amount of gates possible. Which is why I have come to this forum to see if I can get this simplified as much as possible.
Somewhat... but not entirely. I've seen them online but I have no formal experience other than reading them.Svein said:Are you familiar with Karnaugh diagrams? ( https://en.wikipedia.org/wiki/Karnaugh_map )
I asked because a Karnaugh map is used for minimizing logical expressions with respect to gates.Crushforce said:Somewhat... but not entirely. I've seen them online but I have no formal experience other than reading them.
Yes, You use the kmap to get the minimum logical expression, you then convert them to nand gates. You can also use the kmap and OLNY find nand gate connectionsjerromyjon said:I think the main point was to use only NAND gates since they can perform the function of any gate...
Sorry, I skimmed and missed that point. And thank you that saves some brain strain!donpacino said:You can also use the kmap and OLNY find nand gate connections
Happens to the best of usjerromyjon said:Sorry, I skimmed and missed that point. And thank you that saves some brain strain!
Crushforce said:Yeah I just realized that, how about this?
Your design is for a 1 bit half adder followed by a 1 bit full adder.Crushforce said:I wanted to ask if there was any way that I could make it with less logic gates?
Baluncore said:Your design is for a 1 bit half adder followed by a 1 bit full adder.
A two bit adder needs a carry input to make it a “full” adder.
Your solution, 4 inputs; in decimal, 3+3 = 6; which needs three outputs.
A full adder, 5 inputs; in decimal, 1+3+3 = 7; which also needs three outputs.
We need to know the rules of the challenge, what is the target technology?
Is there a carry input to the first stage?
Is the design restricted to using NAND gates only?
Can gates with three or more inputs be used?
c1 ' carry input, bit value 1
a1, b1 ' data inputs, bit value 1
a2, b2 ' data inputs, bit value 2
c2 ' internal carry, bit value 2
s1, s2, s4 ' sum output terms, s4 is carry out
t11 = NAND( a1, b1 )
t12 = NAND( t11, b1 )
t13 = NAND( a1, t11 )
t14 = NAND( t12, t13 )
t15 = NAND( c1, t14 )
t16 = NAND( t14, t15 )
t17 = NAND( c1, t15 )
s1 = NAND( t16, t17 ) ' sum, bit value 1
c2 = NAND( t11, t15 ) ' internal carry
t21 = NAND( a2, b2 )
t22 = NAND( t21, b2 )
t23 = NAND( a2, t21 )
t24 = NAND( t22, t23 )
t25 = NAND( c2, t24 )
t26 = NAND( t24, t25 )
t27 = NAND( c2, t25 )
s2 = NAND( t26, t27 ) ' sum, bit value 2
s4 = NAND( t21, t25 ) ' sum or carry out, bit value 4
To design a 2-bit full adder using only NAND gates, you will need to use a combination of logic gates and Boolean algebra. First, you will need to break down the 2-bit addition into smaller parts, such as the sum and carry calculations for each bit. Then, you can use NAND gates to implement these calculations according to Boolean expressions that represent the logic behind each calculation.
Using only NAND gates in the design of a 2-bit full adder can reduce the number of components needed, which can save space and cost. It also allows for simpler circuitry and easier troubleshooting, as NAND gates are universal gates that can be used to implement any other logic gate.
The truth table for a 2-bit full adder using only NAND gates will have two inputs for each bit (A and B), two outputs for each bit (Sum and Carry), and four rows to represent all possible combinations of inputs. The truth table will show the output values for each combination of inputs, and these values can be used to determine the Boolean expressions needed to implement the 2-bit full adder using NAND gates.
Yes, you can use other types of logic gates in addition to NAND gates in the design of a 2-bit full adder. However, using only NAND gates can simplify the design and reduce the number of components needed. You can also use other universal gates, such as NOR gates, to implement a 2-bit full adder.
To test the functionality of your 2-bit full adder design using only NAND gates, you can use a circuit simulator or a prototyping breadboard to physically build the circuit. Then, you can input different combinations of binary numbers and compare the output with the expected results from the truth table. You can also use Boolean algebra to verify the functionality of your design.