Difference between Flip-flop and latch

[Charismaztex]

Hi,

I've read that some authors do not make the distinction that latches are level triggered (with clock of course) and flip-flops are edge-triggered and synchronized by the clock.

I am wondering, are there level-triggered flip-flops? My lecture notes says
that this

is a level-triggered flip-flop as opposed to 2 rectangular blocks with dynamic-input indicators which would indicate edge triggering (what's the difference between this D master-slave flip-flop in the image and a, say, negative edge triggered D flip-flop as both changes occur at end of pulse?). Actually, are all D negative or positive edge triggered flip-flops master-slave flip-flops?

My understanding now is: (2 rectangular blocks as a whole) is an SR master-slave flip-flop and each rectangular block is a latch (which can be level triggered). Postponed output indicator indicates that output signal changes at end of, in case of SR master-slave flip-flop, edge of pulse (end of positive pulse for first block in image and end of negative pulse for second). Hence this implies that the master-slave flip-flop (if 2 rectangles or latches are considered as one flip-flop) or any flip-flop is edge triggered.

Is my understanding correct? I know the thinking is a little muddled so please help me clear it up and I think my lecture notes may be wrong. What's the verdict?

Thanks!

 

[Blibbler]

There are a few different types of flip-flop and a latch copies and holds the input.

Some other flip-flops toggle between values.

As far as I can recall 9and I haven't bothered to search by the way) there are J and K types as well as D type and SR (set reset) might be one of these...sorry not be more use, but I started typing brimming with confidence which appears to have been inappropriate!

 

[Jaynte]

a flip flop is constructed by two latches and can be triggered both on falling edge or rising edge of any signal, i.e. a clock but it is always triggered.

a D-flip flop will show the input on the output when c goes high if it is triggered on rising edge and when c goes low if triggered on falling edge.

a Latch is transparent and will show the input on the output when clock is low and will be locked when the clock goes high for rising edge triggered latch. But if you place two latches in serial it will not be transparent.

You should look at the functional tables for D, T SR and JK flip flops to get a better understanding. And also look at a schematic for a flip flop to really understand what happens.

Also the output of a flip flop will not show the result imidiatly on the triggered edge, it will take some time before the data is stable due to delay.