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Homework Help: Timing diagram of flip flop and d-latch

  1. Mar 1, 2015 #1
    Tried using the template, had to put pictures because this concerns a diagram question! sorry guys!

    1. The problem statement, all variables and given/known data

    Consider the circuit shown in the figure below which consists of a positive edge triggered flipflop with selective load capability (identified as MICK) and a level sensitive D-type latch (labelled as KEITH). There is an input bus (consisting of a single wire) , an output bus, and two tri-state buffers. Complete the timing diagram which is included at the end of this question. Indicate in the provided timing diagram the behavior of the output of the flip-flop and the latch (q_mick and q_keith) as well as the behavior of the output bus between the indicated “start” and “end” times. Use the symbol “Z” to denote the state of the output bus when it is in the high impedance (tri-state value). In the given diagram, it is assumed that the initial value of q_mick is logic ‘0’ and that the initial value of q_keith is logic ‘1’. Note also that the timing diagram intentionally contains a fatal design error. You are to explain in words the nature of this design error. Use the word “FIRE” in the appropriate place in the timing diagram to indicate the state of the output bus at the interval in time during which the design error occurs.



    Timing diagram to complete:


    Answer ( which I do NOT understand, the answer itself and don't even get me started on the handwritting! haha):


    2. Relevant equations

    I really don't think I need equations in this problem

    3. The attempt at a solution
    I can't even answer the question, not even a bit, I have so many questions concerning the question itself:

    1) positive edge triggered flipflop with selective load capability --> what is that? I mean it is triggered on rising edge but selective load capability? I don't know what that stands for.

    2) level sensitive D-type latch --> I know what a D-type latch is but "level sensitive"? I mean I've never hear of that too ( is it even relevant to the problem?)

    3) Also if MICK is positively triggered, why doesn't it fall on the falling edge of the clock?

    4) As for the q_keith, why is it only triggered when the input is turned to 1? I thought, again it would trigger with the clock ( I have a feeling I'm mixing up a concept here)

    5) I know a tri-state buffer "buffs" the current ( hence the name - unless I'm wrong). But how do you know whether or not "the output bus when it is in the high impedance"? Does it just mean when the output is 1?

    6)Why can't en_mick/keith be both enabled at the same time? I thought they are both different output so they can behave differently.

    7) what on earth is id_mick? Is it even relevant to the question?

    Sorry for the long question guys
  2. jcsd
  3. Mar 1, 2015 #2


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    I have changed the order of your questions to make it easier to understand..

    The selective load signal tells the latch to use or ignore the rising edge of the clock. With selective load =1 the D input is sampled on the rising edge. If selective load =0 the latch ignores clock edges and Q stays at the last value regardless of changes to D.

    That's the selective load signal for Mick. Edit: I believe it's "ld_mick" short for "load_Mick" (not "id").

    The difference..

    Edge Triggered latches: With an edge triggered latch the input D is sampled and let through to the Q output on the rising edge. You have to maintain or hold the D input for a short time after the rising edge. This is called the hold time but after that changes to D do not effect Q.

    Level triggered: With a level triggered latch the Q output follows changes to the D input any time the clock is high. So D is let through to Q on the rising edge but you have to maintain the D input until the clock goes low again or Q will change.

    Because the selective load signal ID_Mick is only =1 for the first rising edge of clock. After that its=0 which means no change. See Q1.

    Kieth is level triggered. See above. So the Q output = In_bus any time clk is high. When clk is low changes to In_bus are ignored and Q is stays unchanged.

    The output of a tristate buffer can be either 0, 1 or Hi Z (hence tri or three state). The output is Hi Z when the enable signal is inactive. In other words when en_Mick = 0 that buffer is Hi z.

    There might be times when Q_Mick = 1 and Q_Kieth = 0. What would happen if they were connected together? A FET in Mick is pulling up and a FET in Kieth is pulling down. Result is a "short circuit" between the supply rails. Well ok it's not exactly a short circuit as FETs still have some resistance when on but you get the idea. Edit: Do you see why the problem statement says to write "FIRE" on the timing diagram :-)
    Last edited: Mar 1, 2015
  4. Mar 1, 2015 #3


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    An example of how the selective load might be used...

    Suppose you were designing a microprocessor using latches to build several 8 bit registers. Lets say the Arithmetic and Logic unit has done a calculation and the result is on the in_bus which is connected to the D inputs of all the registers. You then need some way to control which register the result is stored in. Some bits of the instruction might be used to tell the logic which register that is. Those bits would be decoded and used to generate the selective load signal for the corresponding register. On the next rising edge of the clock the result is stored in the selected register. All the other registers would ignore the new data and maintain their previous values.
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