Do microcontrollers have cache?

[EvLer]

Do microcontrollers have cache?

 

[berkeman]

Depends on the uC. RISC architectures typically use cache, but I don't think it's common for CISC architectures. Not sure about that though. Do you have a uC in mind?

 

[EvLer]

no, not really, just was wondering when someone asked me i could not think if they do or not. But thanks! now at least i know that they may or may not.

 

[EvLer]

one more question: what is usefulness in NOT having cache or what is used in place of it?
Thanks!

 

[berkeman]

I googled risc cisc cache tutorial, and got some great hits. Here's the first one:

http://www.laynetworks.com/RISC.htm

The goal with a RISC architecture is to have fewer and simpler instructions in the instruction set. As they say on that web page, ideally your RISC processor should be able to execute one of its instructions per clock cycle, versus many cycles in traditional CISC processors. In a traditional CISC processor, you spend several minor cycles fetching the first part of the instruction, then figure out if there is more to fetch (multi-word instructions like long jumps or add immediates), then mess around some more, then finally perform the instruction.

But since the RISC architecture is aimed at executing one simple instruction per clock cycle, it can gobble up data much faster than a CISC processor, so internal fast cache is used as a pipeline to keep the RISC engine running at full speed. But as with any pipeline architecture, if you get an unanticipated branch, you have to empty the pipe and start re-filling it, which lowers the effective speed of the processor.

You can have several levels of cache, with the smallest and fastest on the processor silicon itself, and an intermediate cache off-chip that is fed by the main RAM section of the motherboard. Since cache needs to be fast, it is expensive to use, and you only use it if you can justify the cost from the performance enhancement angle. With a CISC processor, you usually just have RAM outside and no justification for pipeline cache.