Efficient CMOS Comparator Circuit for PWM Experiments with Sawtooth Generator

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The discussion focuses on a CMOS comparator circuit used for PWM experiments with a sawtooth generator. The circuit employs PMOS transistors M3 and M4, with M9 and M1 configured in a saturation-load NMOS setup, ensuring they operate in the saturation region to provide a constant current source. The behavior of the circuit is influenced by the varying inputs Vsaw and Vin, which determine the operational regions of M3 and M4. Additionally, M5 and M6 also function as constant current sources, affecting the current distribution between M4 and M5 based on their gate voltages. Understanding these dynamics is crucial for optimizing the comparator's performance in PWM applications.
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I have been experimenting with PWM circuits and I came across this CMOS comparator that seems to work well with the sawtooth generator I am using. I feed a sawtooth wave to the gate of the PMOS M3 transistor and the reference voltage I am comparing to Vin the PMOS M4.

I noticed that the PMOS's M9 and M1 are in a saturation-load NMOS setup. If I recall correctly this means they are both operating in the saturation region which generates a constant current source.

Vsaw and Vin seem to be controlling which region M3 and M4 will be operating in.

Can anyone help me in understanding the rest of this or if I completely off can someone explain to me how this is operating?

Thanks for any help!
 

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Notice that M5, M6 are also a constant current source. As Vsaw and Vin vary, the current sharing of M4, M5 shifts; that is, the sum of the current thru M4, M5 stays the same but more current will flow thru one or the other depending on their Gate voltages.

Since the output stage, M7,8,11, is controlled by M4, the output depends on the current thru M4.

M10 is just a current source for M7.

https://www.physicsforums.com/attachments/circuit-jpg.66076/
 
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