The discussion centers on selecting a final semester project utilizing CMOS VLSI technology, with a specific focus on using Tanner Tools for design. Participants emphasize the necessity of designing a CMOS VLSI circuit, suggesting that Arduino-based projects could fit the criteria. Key questions arise regarding the complexity of the project, the use of Verilog for coding, and the potential for FPGA targeting. The conversation highlights the importance of defining project specifications and complexity to ensure a successful outcome.
PREREQUISITESStudents in electrical engineering, particularly those focusing on VLSI design, as well as educators and professionals seeking project ideas in CMOS technology.
Thanks for responding .We have to use CMOS VLSI in our project.Baluncore said:
What ideas have you considered so far? Are you going to code up your application using Verilog and target an FPGA? If so, which FPGA and what design tools are you going to use?MAHESH BABU SANNIDHI said:
thanks for your response.Borek said:
I'm not getting any ideas about this. we are going to use tanner tool for the VLSI designberkeman said:
Tanner Tools is IC design software. So you are really going to design and lay out an IC? How many gates are you targeting? What geometry (minimum feature size)? Do you have an IC fab on your campus that you will use to actually fab some first articles of your IC? (Some universities are lucky enough to have that available -- the University of Michgan did back when I went to graduate school in the early 1980s.)MAHESH BABU SANNIDHI said:
That is hard to believe. This is your schoolwork project, after all, so you need to show some effort at brainstorming some IC project ideas. What is the most complex circuit that you have designed so far? Do you know what a Finite State Machine is? Have you designed circuitry using Verilog or VHDL before? Have you designed any PAL or FPGA based circuits? What kinds?MAHESH BABU SANNIDHI said:
That's also a bit hard to believe. One of my EE friends in graduate school had such an assignment, and the requirements were *very* detailed on how complex it needed to be, what kinds of IP could be used, what sorts of building blocks should be included, the geometry of the in-house fab (along with the associated design rules), etc. An open-ended assignment would be too hard to manage and grade as an instructor.MAHESH BABU SANNIDHI said: