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Help making a digital delay circuit

  1. Oct 19, 2009 #1
    right... i need to make a programmable digital delay circuit that can delay a pulse by a few nanoseconds. sorry if any of the following info is vague, im only an apprentice and i have taken this on as a college project, but the poduct will be used at work in a calibration lab, but i am not too knowledgable as of yet so im very much an amateur.

    anyhoo, what it will be used for is calibration of TDR's/cable testers. i need it to be able to take in a pulse and delay it by a programmable amount, down to about a 10ns delay. i know a product exists for this, but buying a product is no fun :) not to mention expensive...
    it will need to take in the pulse from the TDR, delay it, and send it back. this will replicate the function of the TDR in real conditions.
    as i mentioned it will need to be programmable, possibly by means of a binary input (so ive been told :s)

    im still in the mind mapping stage, if you want to get technical then great, but even small pointers will be greatly appreciated. circuit schematics, specific ICs, i will accept anything

    thanks in advance
     
  2. jcsd
  3. Oct 19, 2009 #2
    The speed of light is about 30 cm, or 1 foot per nansosecond, equivalent to about 8 inches of RG-58. We used to use mechanical switches to make switchable delay-line boxes (e.g., 10, 20, 40, 80 ns). 80 ns cable is ~[STRIKE]64[/STRIKE] 640 inches. Sounds kind of old fashioned, but coaxial cable has better fidelity than most digital delays.
    Bob S
     
    Last edited: Oct 19, 2009
  4. Oct 19, 2009 #3

    berkeman

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    Staff: Mentor

    Welcome to the PF. Another way to do it is with a clocked shift register, where you can mux the different outputs to a single output. This lets you select how much delay the signal has. Run your shift register at some frequency (depending on how much power you are willing to burn in your circuit), say 100MHz to get your 10ns resolution. You will need to use fast logic and be careful in your PCB layout at these frequencies. Might be easiest to do on a 5ns CPLD or FPGA...
     
  5. Oct 19, 2009 #4
    Be careful of ripple-carry delays in shift registers unless they are synchronous. You could use synchronous presettable up down counters. Compare the 7490 and 74190 to compare the concept of synchronous and non-synchronous counters. Look at the 74F161 -74F163 100-MHz presettable counter. See:
    http://www.fairchildsemi.com/ds/74%2F74AC163.pdf [Broken]
    Bob S
     
    Last edited by a moderator: May 4, 2017
  6. Oct 19, 2009 #5

    berkeman

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    Staff: Mentor

    I definitely was talking about synchronous shift registers, not counters. The clock signal goes to all FFs. It may take a clock tree architecture to distribute the clocks, depending on the max number of delays he needs, and the fanout of the clock drive gates.
     
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