Engineering Help with CMOS Circuit Truth Table

AI Thread Summary
The discussion focuses on creating a truth table for a CMOS circuit, with a specific circuit diagram referenced. The user is uncertain about the values for the transistors P1, P2, N1, and N2, and seeks confirmation on their initial truth table setup. It is clarified that applying a '1' to an NMOS gate turns it on, while a '0' does the same for a PMOS, leading to an output that inverts the input. Additionally, the complexity arises from the source and drain connections of the PMOS transistors not being uniform. The conversation concludes with encouragement and a hope for clarity in the user's understanding.
majestrooo
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Hope this is the right place for this thread.

Homework Statement



Hi I need help with the truth table for a CMOS circuit.

http://www.isk.kth.se/~william/dd/agda/bild/cmos/mos903.gif

Homework Equations



Truth table and

What type of circuit is this? But I guess that's easy to
answer after setting up the truth table. Right now, I'm not even sure
if the values for P1,p2,n1,n2 are correct.

The Attempt at a Solution



Is this correct?

IN
0 0 -> On: P1,P2, Off: N1,N2 OUT: ?
0 1 -> On: N1,P2, Off: P1, N2 OUT: ?
1 0 -> On: P1,N2, Off: N1,P2 OUT: ?
1 1 -> On: N1,N2, Off: P1,P2 OUT: ?
 
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I believe you're on the right track. Assuming correct biasing, application of a '1' to the gate of a NMOS will turn it on, and pull drain to ground (assuming source is at ground), while application of a '0' to the gate of a PMOS will turn it on, and pull the drain to VDD.

The simplification here is that the output is in a push-pull configuration with PMOS and NMOS gates tied together (so it'll just invert whatever is at their shared gate).

The (slight) complication is that the source terminals of P1 and P2 are not both connected to VDD, nor are their drain terminals both connected to the push-pull CMOSs. But just remember what the source-drain impedance of a cut-off MOSFET is.

Hope this helps, and good luck!
 

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