Finding the CMOS transistor width ratio

In summary, the conversation discusses the calculation of the ratio of Wp/Wn for a CMOS inverter in a chain of circuits to achieve the least delay time. The minimum delay time is given by the formula B=sqrt(Rd_p/Rd_n), where Rd is the dynamic resistance of a transistor. The conversation also mentions the calculation of the maximum short circuit current for a given Vdd. The solution involves calculating the resistances and dividing them to determine the value of B, which is then used to calculate Wp. The conversation ends with a request for verification of the solution.
  • #1
diredragon
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Homework Statement


Calculate the ration of ##w_p/w_n## if n and p transistors in CMOS inverter necessary for the least delay time ##t_p## if the circuit is used in a chain of circuits.
a) What is ##w_p## in that circuit if you're given :
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b) Calculate the maximum short circuit current if ##V_{DD} = 3.3V##.

Homework Equations


3. The Attempt at a Solution [/B]
The minimum delay time for a CMOS circuit in this scenario is given if ##B## which is ##B=\frac{\frac{w_p}{L_p}}{\frac{w_n}{L_n}}## equals ##B=\sqrt{\frac{Rd_p}{Rd_n}}## where ##R_d## is dynamic resistance of a transistor calculated from a formula ##R_d=\frac{3}{4}\frac{V_{dd}}{I_{dsat}}*(1-5/6λV_{dd})##. So all i need to do is calculate both resistances divide them and get what ##B## equals so i can calculate ##w_p##.
For a N-Mos transistor ##I_{dsat}=1/2*\frac{μ_nC_{ox}w_n}{L_n}*(V_{dd} - V_t)^2## (Just for easier calculation I'm ignoring the short canal and effects of ##E_{cn}##. Putting all into equation and divind the parts which are the same i get:
##\frac{Rd_p}{Rd_n} = 270/70\frac{w_n}{w_p}## and if i use that ##w_p = B*w_n## since the lengths are the same i get ##\frac{Rd_p}{Rd_n} = 270/70\frac{1}{B}## and finally taking a square root and extracting ##B## i get that ##B=1.56##. This makes ##w_p = 624nm##. I have no way of checking if this is correct as no solution is given. Could you check and possibly correct the mistakes i made?
 

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  • #2
I don't understand what your doing but if I had to do it Id start with the Miller capacitance of the mos being the dominant factor, I had to look up permutivitty on wiki, maybe that will help as all I knew it from was transformers.
 
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Related to Finding the CMOS transistor width ratio

1. What is the CMOS transistor width ratio?

The CMOS transistor width ratio refers to the ratio of the width of the p-channel transistor to the width of the n-channel transistor in a complementary metal-oxide-semiconductor (CMOS) circuit. This ratio plays a crucial role in determining the performance and power consumption of the circuit.

2. Why is the CMOS transistor width ratio important?

The CMOS transistor width ratio affects the speed and power consumption of a circuit. A larger width ratio results in faster switching speeds but also increases power consumption. On the other hand, a smaller width ratio reduces power consumption but can lead to slower switching speeds.

3. How do you determine the appropriate CMOS transistor width ratio?

The appropriate CMOS transistor width ratio is determined through a trade-off analysis between speed and power consumption. Factors such as the desired operating frequency, power budget, and circuit design constraints are taken into consideration to determine the optimal width ratio.

4. What are the typical values for the CMOS transistor width ratio?

The CMOS transistor width ratio can vary depending on the specific circuit design and application. However, a commonly used ratio is 2:1, where the p-channel transistor is twice as wide as the n-channel transistor. Other ratios such as 3:1, 4:1, or even 1:1 may also be used depending on the circuit requirements.

5. Can the CMOS transistor width ratio be adjusted after the circuit is fabricated?

No, the CMOS transistor width ratio is determined during the circuit design phase and is physically implemented during the fabrication process. It cannot be adjusted after the circuit is fabricated, so it is important to carefully consider and optimize the ratio during the design stage.

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