Help with computer engineering problem

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Discussion Overview

The discussion revolves around a computer engineering problem related to cache memory, specifically focusing on the definitions and implications of 2-way and 4-way caches. Participants explore the effects of these cache types on the problem at hand, as well as the calculations for tag lengths.

Discussion Character

  • Homework-related, Technical explanation

Main Points Raised

  • One participant expresses difficulty in approaching the problem and seeks guidance.
  • Another participant emphasizes the need for the original poster to demonstrate effort by defining 2-way and 4-way caches and discussing their effects.
  • A participant claims to have calculated tag lengths, stating 15 bits for part a and 14 bits for part b, but does not provide the methodology behind these calculations.
  • A follow-up request is made for the participant to show their working process for the calculations provided.

Areas of Agreement / Disagreement

There is no clear consensus on the solutions to the problem, as participants are still discussing definitions and calculations. Multiple viewpoints and requests for clarification remain present.

Contextual Notes

The discussion lacks detailed definitions of 2-way and 4-way caches, as well as the specific assumptions or parameters used in the calculations for tag lengths.

imixerik
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Homework Statement
Consider a system that can host 64 GB of memory and has 8MB of L3 cache. Suppose that each cache line contains 4 chunks, each of size 16B.

a) Assuming 4-way associative cache, what are the lengths (in bits) of the following: tag, cache index, and block offset?

b) How does this change for a 2-way cache?

c) Suppose that if L3 is organized as 2-way, the access time is 20 cycles, but increases to 22 cycles if organized as 4-way, but the miss probability from L3 decrease from 12% to 10%. Suppose that the misses from L3 go to memory, and the average memory latency is 64 cycles. State which option is better and why.

d) Now suppose that the L2 cache can be organized as direct map or 4-way. In the first case, the L2 limited CPI (i.e., CPI if there is no miss out of L2) is 3.5 and MPI out of L2 is 0.08. In the second case, the CPI increases to 3.8 but the MPI is 0.06. Determine the best configuration for this system by considering all four possibilities: (i) DM L2, 2-way L3, (ii) DM L2, 4-way L3, (iii) 4-way L2, 2-way L3, and (iv) 4-way L2, 4-way L3.
Relevant Equations
Not sure what equations to use
Have been trying to figure out this problem for quite some time but don't know how to approach it.
 
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You need to show some effort on your schoolwork questions before we can offer tutorial help.

Start by defining 2-way and 4-way caches for us please. What effects will the differences have on this problem?
 
berkeman said:
You need to show some effort on your schoolwork questions before we can offer tutorial help.

Start by defining 2-way and 4-way caches for us please. What effects will the differences have on this problem?
Hey,

I worked through the problem and would like to believe I reached the correct solution for a and b. For a, i got 15 bits for the tag length and for b, i got 14 bits for the tag length.
 
imixerik said:
Hey,

I worked through the problem and would like to believe I reached the correct solution for a and b. For a, i got 15 bits for the tag length and for b, i got 14 bits for the tag length.
Great! Can you show us how you worked the numbers to get those answers? :smile:
 

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