High-k/Metal gate transistors going into production at Intel, IBM and AMD

[Hans de Vries]

After many years of research, micro processors will be build of transistors
using different materials as have been the case in the past 40 years:

"Gordon Moore, 78, came out of retirement, where he spends some of his time
in Hawaii, to issue a statement Friday about the Intel team's innovation.
He said Intel's use of high-k and metal materials ``marks the biggest change
in transistor technology'' since Intel's pioneering use of polysilicon in 1969."

Transistor scaling could not continue when the isolating SiO2 dielectric
that separates the Gate of CMOS transistor from the conducting Channel
became 1.2 nm or just five molecules thick. Experimental transistors which
reached a thickness of 0.8 nm were to leaky to be used in production.

The solution to continue scaling now is to use materials which have a far
higher dielectric constant so that the isolating layer can be much thicker.
Hafnium based compounds are used while the traditional material used for
the gate, polysilicon, is replaced by metals.

Rather, surprisingly, after many years of difficult progress in research, both
Intel and IBM/AMD now announced that this new technique will go into
mass production for their micro processors. Intel will roll out chips at the
end of the year while IBM and AMD plan to do so in mid 2008.

http://www.mercurynews.com/mld/mercurynews/16558220.htm
http://www.intel.com/technology/silicon/45nm_technology.htm?iid=homepage+42nm


Regards, Hans

 

[Gokul43201]

This is written a little misleadingly (from the first link above):

The two companies have different approaches to their use of high-k metal gates.

Doherty, the Envisioneering analyst, said IBM integrates their high-k metal inside the silicon, where Intel's development is on top of the silicon.

What is "high-k metal"? By using that terminology, they're making it look like they're using some new kind of metal called 'high-k metal', rather than a combination of a high-k dielectric and a metal. It would be less confusing if they just used a forward slash between 'high-k' and 'metal'.

I think this is marlon's area, and he's been working on it for a few years now, as have all the big chipmakers, from Intel to Micron and Samsung. I was expecting the engineering breakthrough to come from the RAM builders.

 

[free_electron]

Samsung 70 nm DRAM uses high-k HfAlO. I think they even changed it at least once.

 

[Hans de Vries]

Technical 45 nm high k / metal gate paper from IBM, AMD, Sony and Toshiba.

http://regmedia.co.uk/2007/01/28/ibmhighk.pdf

High-Performance High-k/Metal Gates for 45nm CMOS and
Beyond with Gate-First Processing

Abstract:
Gate-first integration of band-edge (BE) high-k/metal gate nFET
devices with dual stress liners and silicon-on-insulator substrates for the
45nm node and beyond is presented. We show the first reported
demonstration of improved short channel control with high-k/metal
gates (HK/MG) enabled by the thinnest Tinv (<12Å) for BE nFET
devices to-date, consistent with simulations showing the need for <14Å
Tinv at Lgate<35nm. We report the highest BE HK/MG nFET Idsat
values at 1.0V operation. We also show for the first time BE high-
k/metal gate pFET’s fabricated with gate-first high thermal budget
processing with thin Tinv (<13Å) and low Vts appropriate for pFET
devices. The reliability in these devices was found to be consistent with
technology requirements. Integration of high-k/metal gate nFET’s into
CMOS devices yielded large SRAM arrays.


Regards, Hans

 

[free_electron]

Samsung 70 nm DRAM uses high-k HfAlO. I think they even changed it at least once.

Actually it was 90 nm design rule but 70 nm gate, but the high-k was AlO/HfO

http://www.micromagazine.com/archive/05/07/chipworks.html

 

[Astronuc]

SciAm has a related article online.

http://www.sciam.com/article.cfm?chanId=sa003&articleId=742A3381-E7F2-99DF-3D54A13380979044

Last week Intel and IBM both announced that they had figured out a way to further shrink the size of transistors, the tiny on-off switches that power computers. The trick, according to Intel, is introducing the metal hafnium into the mix—an addition that marks the first major change in transistor materials in four decades. Hafnium-based computer circuits would likely be denser, faster and consume less power than existing microprocessors.

"It's a very, very significant event," says electrical engineer Carlton Osburn of North Carolina State University, member of a research team that studied hafnium and other advanced transistor materials. "This directly addresses one of those grand challenges" in semiconductor manufacturing.

. . . In its transistors, hafnium oxide plays the role of the so-called gate dielectric, an insulating layer that separates the transistor's electrode from its silicon channel for carrying current. . . .

To overcome this obstacle, chipmakers had to determine how to replace silicon dioxide with so-called high-k materials like hafnium and zirconium. A material's performance as a gate dielectric depends on its thickness and its k-value, or dielectric constant, which reflects its ability to store a charge. Because hafnium has a higher k-value than silicon dioxide, it should be able to do the same or better job at a thickness that prevents leakage. That advance would allow Intel to shrink the smallest dimension of its transistors from today's 65 nanometers to a svelte 45 nanometers, keeping the furious pace of transistor miniaturization on its expected track.

. . . .

I was initially puzzled by the use of high-k, since I use it for thermal conductivity (rather than the dielectric constant). But then I realized that this was microelectronics and likely 'k' had to do with another property, which is explained in the article.

 

[Hans de Vries]

Actually it was 90 nm design rule but 70 nm gate, but the high-k was AlO/HfO

http://www.micromagazine.com/archive/05/07/chipworks.html

Very innovative device. Also one of the very first devices to use ALD,
Atomic Layer Deposition, in a high volume production process.

Depositing single atom thick layers one at a time, ALD tutorial:
http://www.cambridgenanotech.com/papers/Atomic%20Layer%20Deposition%20tutorial%20Cambridge%20NanoTech%20Inc.pdf

Rather rudimentary ALD wikipage: http://en.wikipedia.org/wiki/Atomic_layer_deposition


Regards, Hans

 

[Hans de Vries]

Of course this is all based on industry wide research, often joint pre-
competitive research in institutes like IMEC (where Marlon is doing his
PHd on this subject) and SEMATEC.

There was a SEMATEC announcement at the same day here:

http://www.sematech.org/corporate/news/releases/20070126.htm

Claiming a high k/ metal gate breakthrough! (Gate first, like IBM,AMD,Sony,Toshiba)

There is also NEC with its 55 nm process:
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=196901943


Regards, Hans

 

[free_electron]

Was wondering whether high-k is overkill (for the time being)? For example, silicon nitride has a dielectric constant that is roughly double that of silicon dioxide, yet it is definitely easier to integrate than the more exotic materials. Could easily get at least a couple of generations out of it. A material with an extremely high dielectric constant (>10) has less scaling effect on EOT (since its electrical thickness is reduced by the large dielectric constant factor), so in fact a mild increase in dielectric constant would make more sense for scaling.