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High speed semiconductor devices

  1. Feb 19, 2006 #1
    can any one explain about high speed semiconductors . how do ge and gaAs can achive those speeds
  2. jcsd
  3. Feb 20, 2006 #2


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    Mostly, it comes down to defect density. With the latest advances in MBE growth, you can make GaAs heterostructures with mobilities as high as a few million cm2/Vs. With Czochralsky or MOCVD, you do not have the same degree of control.
  4. Apr 2, 2006 #3
    The question is a bit vague, but materials such as Ge, GaAs, and InP are inherently "faster" than the Si traditionally used in electronics. A traditional measure of a semiconductor material's ability to respond to an electric field is the mobility.

    Some typical values for electron mobility in (cm^2/V-s)
    Si: 1500
    Ge: 3900
    GaAs: 8500
    InP: 5400

    As mentioned, crystal quality is a huge factor in the actual measurable mobility. Most published figures are actual rather than theoretical values.

    A greatly simplified way to think of it (***and admittedly not totally correct) is that as you put bigger atoms in the crystal, the increased number of electron shells will shield the free electron from the nuclear charge, thereby allowing it move "faster" through the crystal.
  5. Apr 2, 2006 #4

    Dr Transport

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    Another reason that these devices are so fast is that they are direct band gap materials, Si is not. The faster of the processes in semiconductors take place at the center of the Brilluoin zone. For example to get to the lowest band gap in silicon, you need a phonon assist (which takes time) whreas in GaAs you don't.
  6. Apr 8, 2006 #5
    Ok, but there IS a reason why Si is used in transistors and NOT Ge. Ge has prospects to replace Si as the CMOS substrate but lots of work needs to be done.

    These caracteristics of Ge itself are not really that important when it comes to CMOS devices. The key parameter is the electrical quality of the interface between Ge and the dielectric that you use (like HfO2 or HfSiO4 in today's research). The contact of Ge and the dielectric will cause the Ge to oxidize and there is your "problem" : the interface does not have the right electron affinities for CMOS operation. Due to the oxidation at the interface, the Ge electron affinity will change when you are close to the interfacial region between Ge and the high k material. Incorrect electron affinities lead to a flatband voltage shift that causes the CMOS transistor to slow down and become more energy consuming (bigger leakage currents). Also, one needs to study the influence of dopants (C,N) and oxidation (especially due to the high k deposition method like Atomic Layer Deposition) onto the interface electrostatics. I have a friend at IMEC who is working on this.

    Last edited: Apr 8, 2006
  7. Apr 8, 2006 #6

    Hans de Vries

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    This is a very interesting area of research. One might wonder if an ALD
    processed ultra shallow layer of Si between the Ge channel and the
    dielectric could do the trick. The big advantage would be compatibility
    with all the work done one high-k dielectrics and metal gates.

    There's lots of work done on SiGe recently, mostly for stress induction
    in the channels to increase hole and electron mobilities in the latest Intel,
    AMD and IBM processors, as you probably know.

    It's about one and two years ago that I've read that some group had
    solved the same problem for GaAs, so that it could be used to build CMOS
    circuits. That would be a big breakthrough indeed. I haven't heard much
    since then however.

    Regards, Hans
  8. Apr 8, 2006 #7


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    Strangely enough, this is a area (albeit, a SMALL area) of research work that I'm doing right now - not for fast electronics, but as a photocathode material.

    While Si is an indirect band gap semiconductor, strangely enough, amorphous Si has characteristics of a direct band gap semiconductor (E vs k dispersion is not well-defined for amorphous material). There have been a spirited research on such thing because this could mean cheaper and easier electronics since Si fabrication and control are well-known, and Si is cheap and abundant.

    Our interest in using it as a photocathode in a photoinjector comes from the fact that Si is very robust, more so than most other semiconductor photocathodes, and have a QE (quantum efficiency) higher than metals. Currently, I am in the process of researching companies that can provide us with samples that are suitable to be used in our facilities. Another project down the line is to see if amorphous Si can be ceseated to produce a negative electron affinity photocathode, which would increase its QE even more.

  9. Apr 8, 2006 #8
    Well, i get your point but it is a bit too optimistic IMO. I mean, replacing the polysilicon gate by a metal gate is a process with a lot of associated difficulties that are far from solved. This is the part of CMOS-problems where i work on for my PhD. I mean, the flatband voltage shift a talked about also occurs when we use a metal gate/high k stack. And even more strangely, the shift is different for both n and p-MOS when you use the same gate and dielectric. Good gate candidates are Ta, Mo, Ru with a HfO2 or HfSiO4 dielectric on top. The gate workfunction at the interface "may" be tuned by C and N incorporation. Especially C looks quite ok.

    Using ab initio DFT simulations i actually try to study the influence of such dopant incorporation onto the interface electrostatics.

  10. Apr 8, 2006 #9
    Besides, you wouldn't wanna bring in a Si layer between Ge and the dielectric for several reasons :

    1) electron mobility of Si lower as Ge
    2) how to control the interface electrostatics with an additional layer in the stack
    3) the presence of an extra capacitance that lowers the CMOS switching speed (this is a detrimental effect that you also have with the polysilicon gate ontop of the SiO2 dielectric)
    4) The ALD process is very accurate with respect to obtaining the correct dielectric thickness after "enough" cycles. But ALD is not used to deposit just Si because there is always going to be oxidation due to the H20 presence.
    5) H20 is very polar and also has an influence on the interface electrostatics. The same problem occurs at the metal gate/high k interface.

    Last edited: Apr 8, 2006
  11. Apr 8, 2006 #10

    Hans de Vries

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    I'm aware of the first 3 points, they are pretty elementary, 1 and 3
    should go away if the interface layer is in the order of a few atoms.
    Important is a very smooth interface since any scattering here gives
    you perfomance loss.

    The point is, as usual, people want to work with what they've got.
    When the high-k /metal gate combination works you want to re-use
    it for SiGe or pure Ge channels. Globally it's a billion dollar investment.
    (plus years in time to market loss if you can't re-use it)

    High k gates won't get used now at initial processes for the 45 nm node
    because of the problems there still are with finding the right gate metals,
    (different ones for n- and p- type Fet's ) There was a lot of optimism
    after initial succeses with NiSi two, three years back or so. As far as I
    know polysilicon gates were given up because of Fermi level pinning.


    Do you see a chance that it gets into second generation 45 nm processes
    or the 32 nm node?

    Regards, Hans.
    Last edited: Apr 8, 2006
  12. Apr 9, 2006 #11
    But that's my entire point : you cannot control the Si deposition that good so that you are certain that the interface is that thin. Again, ALD cannot be used for Si deposition only.

    I know.

    I know that and i am not objecting against that. I am objecting against your idea that you put in a Si ALD deposited layer to mimic the classic Si substrate.

    Nitridation of the gate dielectric is already used and successful (ie with right CV curves) CMOS devices have already been constructed.

    Besides, we know what gate materials to use, the problem is to control the interface electrostatics. For example, Ta can be used for both n and p MOS.

    Indeed, but this phenomenon also occurs in the metal gate high k gate stack.

    Generally FLP is defined as the proces where the apparent (ie close to the high k/metal gate-interface) Fermi level of the gate gets fixed at a certain value due to chemical interactions over the interface. This shift in FL leads to a Workfunction shift (since the WF is the difference between the FL and the average of the electrostatic potential over the interface).

    High K /metal gate SHAL be used in 32 nm CMOS technology. After that, the carbon nanotubes transistors (CNT's) will appear. :)

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