How Can a D-Type Flip Flop Handle Simultaneous High Inputs?

[transgalactic]

http://img329.imageshack.us/my.php?image=39501432oa1.jpg

if one of them was 0 then no problem because the other wire value doesn't matter
but here we have both 1
if i look on one of the NANDs gates we have one input of 1
and the other input value is unknown because it comes from the resolt of the other gate
which has the same problem

how to solve it??

 

[ranger]

When SET = RESET = 1, there are two likely outputs of our RS NAND latch. We can have Q = 0 and Q(not) = 1. In this case, the input to the lower NAND gate is 0 and 1, which gives Q(not) = 1. The inputs to the first NAND are both 1 which makes Q = 0.

The second possibility is to have Q = 1 and Q(not) = 0. The same analysis used above can be applied for this situation.

So which situation occurs first? This depends on what has occurred previously at the inputs.