How Can I Resolve Implementation Errors with a 4-bit 4 to 1 Mux in Xilinx?

[mossfan563]

Homework Statement

Pretty much, I'm trying to make a 4-bit 4 to 1 mux using gates.
However, I'm having problems trying to make it.

Homework Equations

None

The Attempt at a Solution

So far this is what I have and whenever I try to implement this in Xilinx, I get errors.
Yes, I know I'm trying to force in a 4 bit input into an AND gate that's only allowing 1 bit and the same can be said for the output of the OR gate at the end.

Not sure what to do here.

 

[berkeman]

You need 4 copies of that circuit, with one input bit per circuit (like a(0), b(0), c(0), d(0))

 

[mossfan563]

Now I have a new problem,

Here's the new mux with all the bits spread out. I know it doesn't look pretty.

This is the top level circuit.

When I try to synthesize the design in Xilinx, I get this Warning which affects my design.

WARNING:MapLib:701 - Signal s0 connected to top level port s0 has been removed.

WARNING:MapLib:701 - Signal s1 connected to top level port s1 has been removed.

Any idea why? If you need more info, let me know.
Basically this circuit, I have a binary input that's put into registers and the output of the registers are muxed and stored.
That way with the s1 and s0, whenever I have s1 = 0 or 1 and s0 = 0 or 1, I get a certain output that's outputted onto LED's of an FPGA.

 

[berkeman]

What does your tool say about Warning 701? There should be a list of errors and warnings somewhere that gives you a bit more info about what each number means...

 

[berkeman]

I just Googled your warning, and got lots of good hits. Could be the direction of s0 and s1, for example. Check out the hit list for clues...

http://www.google.com/search?source...lz=1T4GGLL_enUS301US302&q=WARNING:MapLib:701+

.

 

[mossfan563]

I still can't see it. Everything looks fine. I can't tell what's wrong...even with the hits using google.

 

[berkeman]

I still can't see it. Everything looks fine. I can't tell what's wrong...even with the hits using google.

I did a search at Xilinx's Knowledge Database, and got a lot of hits for this type of warning:

http://xgoogle.xilinx.com/search?ge...tus:archive&q=WARNING:MapLib:701&lang2search=

In general, the problem seems to come up because there is a naming problem, or a missing connection that makes the tool think there is no reason to keep the signals around.

There are some suggestions in the hits at Xilinx on what to look for in the MAP and other files. If you can simplify your circuit down to something that only connects s0 from the top level down to something simple in the lower block, that may help you find the problem.

Have you checked the directions of all of the signals and port connections?