Designing a 4-Bit Multiplier using Basic Digital Logic Components

[DFZXA]

Homework Statement

Begin the design of the multiplier by adding more detail to the block diagram. The parts
available for your design are

• D Flip-flops (74LS74A)
• 1 4-bit Up/Down Counter (74LS169)
• 1 4-to-1 MUX
• 1 4-bit Adder (74LS283)
• 2 4-bit Parallel Shift Registers (74LS194A)
• Various NAND/AND/OR/NOT gates

Basically need to design a 4 bit multiplier using these parts. The block diagram that is referred to is just showing how everything connects up.

Homework Equations

n/a

The Attempt at a Solution

My attempt is in a file below because I thought that would be the best way to show it. I know it said not to use pictures in the rules, but I think it's ok for this right? My screen print cut off the very bottom wire, so yeah I used paint to put it back in sorry about that. My basic problem here is The D flip-flop that goes into the shift register keeps outputting high impedance. I tested this using 1011 as the multiplicand and 0111 as the multiplier. I'm also designing this in Allegro Design Entry.

 

[berkeman]

Homework Statement

Begin the design of the multiplier by adding more detail to the block diagram. The parts
available for your design are

• D Flip-flops (74LS74A)
• 1 4-bit Up/Down Counter (74LS169)
• 1 4-to-1 MUX
• 1 4-bit Adder (74LS283)
• 2 4-bit Parallel Shift Registers (74LS194A)
• Various NAND/AND/OR/NOT gates

Basically need to design a 4 bit multiplier using these parts. The block diagram that is referred to is just showing how everything connects up.

Homework Equations

n/a

The Attempt at a Solution

My attempt is in a file below because I thought that would be the best way to show it. I know it said not to use pictures in the rules, but I think it's ok for this right? My screen print cut off the very bottom wire, so yeah I used paint to put it back in sorry about that. My basic problem here is The D flip-flop that goes into the shift register keeps outputting high impedance. I tested this using 1011 as the multiplicand and 0111 as the multiplier. I'm also designing this in Allegro Design Entry.

Welcome to the PF.

-1- Can you post the "block diagram" stage of this design? That will save a lot of time for potential responders

-2- All unused inputs should be tied off high or low (whichever is appropriate). It is bad form to leave unused inputs floating. That may or may not affect your simulation results (depending on the simulator), but in any case, it is bad design practice to leave inputs floating.

-3- What is the thin blue line at the left of the schematic connecting in parallel to the intended input to those gates?

-4- Can you post the state diagram and truth table that you are using to design this?

 

[DFZXA]

Welcome to the PF.

-1- Can you post the "block diagram" stage of this design? That will save a lot of time for potential responders

-2- All unused inputs should be tied off high or low (whichever is appropriate). It is bad form to leave unused inputs floating. That may or may not affect your simulation results (depending on the simulator), but in any case, it is bad design practice to leave inputs floating.

-3- What is the thin blue line at the left of the schematic connecting in parallel to the intended input to those gates?

-4- Can you post the state diagram and truth table that you are using to design this?

Oh sorry this actually wasn't my completed design something must have screwed up when I transferred it to my laptop. My real design is attached. Block diagram also attached I didn't think it would be useful to see. My TA told me to ignore the controller since my group members dropped the class, so I'm just focused on doing the multiplier part. I'm not sure what blue line you're referring to sorry it all looks pinkish red to me. I haven't really used a state diagram or truth table to make this I kinda just thought about what made sense in my head. I can write one up tomorrow, but I have to keep the light off right now so my roommate can sleep. I'll add some more information though my carry out from the adder is 0 for the first few clock cycles, but the d flip flop stays at high impedance. Shouldn't Q be 0 if D is 0 for a clock cycle? Also the DSTM attached to U1, U4, and U7 are used to just give a 0 to 1 input, so that it properly clears it instead of just outputting high impedance right away.

 

[berkeman]

The connections to the inputs to the "1" side of U2 look to be messed up...

 

[DFZXA]

The connections to the inputs to the "1" side of U2 look to be messed up...

You're right I did not have it that way when I tested the circuit though. I remade the inputs when I transferred it to my laptop and that's the reason for the error there I have now fixed the mistake on my laptop, but I still get the same result as before. My teachers assistant can't even figure it out now.

 

[pranjal091994]

I am not so sure about the answer but I would recommend that you use a software called ISIS proteus. It helps a lot with real time simulations. I made basic circuits with it.