How Can You Create a NOT Gate Using a NAND Gate?

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Basic Electronic Gates Question...

Homework Statement



Demonstrate, via a proper scheme, how can you realize a gate from type NOT, through a single gate from type NAND with two entries?


The Attempt at a Solution



http://img208.imageshack.us/img208/6093/image201202080001.jpg

I got it, right?
 
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Yes, the electronics is right. The translation is a bit awkward:
Demonstrate, via a proper scheme, how can you realize a gate from type NOT, through a single gate from type NAND with two entries?
Demonstrate how to realize a NOT gate using a two-input NAND gate. :smile:

You might be able to think of another slightly different way, still using a two-input NAND gate.
 


Sorry about the translation, it's hard translating technical stuff sometimes! :) Much appreciated.

You might be able to think of another slightly different way, still using a two-input NAND gate.

Hmmm, I can't come up with anything...any clues?
 


The scheme you've shown imposes a double load on whatever is supplying signal A. This often is inconsequential, but sometimes it may be undesirable. There is an arrangement that imposes just a single load.
 


There is an arrangement that imposes just a single load

The problem is that I am asked that the NAND gate has two entries (is that what you mean by load?) so I can't change it to one entry.
 


The NAND gate has two inputs. Each input (in general) requires current and this current has to be supplied from wherever signal A is coming from. By connecting signal A to two inputs of your NAND gate the source of signal A is being asked to supply double the current that it would if you connected to just one input of the NAND gate.
 


Hi FP :smile:
I believe what NascentO is trying to get at,
is something you will also note on the hyperphysics site,
under NAND gate operations.
(You can also find it on wikipedia but hyperphysics is a very fine reference).