How to Choose TVS Diodes for ESD Protection?

  • Thread starter Thread starter saad87
  • Start date Start date
  • Tags Tags
    Diodes Protection
Click For Summary
SUMMARY

This discussion focuses on selecting TVS diodes for ESD protection in a cable continuity tester circuit utilizing CPLDs and MOSFETs. The primary concern is protecting the CPLD's I/O pins, which can be damaged by voltages exceeding 4V. Participants recommend using a TVS diode with a standoff voltage of 3.3V to ensure adequate protection while considering the capacitance of the diode to avoid slowing down the circuit. Additionally, it is noted that while the input side should be protected, the output may not require additional protection due to the fast discharge capability of the TVS diode.

PREREQUISITES
  • Understanding of ESD protection principles
  • Familiarity with TVS diodes and their specifications
  • Knowledge of CPLD and MOSFET operation
  • Basic circuit design involving logic levels and signal integrity
NEXT STEPS
  • Research TVS diode specifications, focusing on standoff voltage and capacitance
  • Learn about ESD testing methods and standards for electronic devices
  • Explore circuit design techniques for minimizing ESD susceptibility
  • Investigate additional ESD protection components, such as varistors and filters
USEFUL FOR

Engineers and designers working on electronic circuits, particularly those involving CPLDs and MOSFETs, who need to implement effective ESD protection strategies.

saad87
Messages
83
Reaction score
0
I'm developing a basic cable continuity tester. Essentially, the circuit drives a test vector onto the cable and reads back the output vector. The output has MOSFETs for buffers/drivers but the input is connected directly to the ICs (CPLD, in my case).

My concern is ESD. Unfortunately, I have very little experience in this area and am seeking advice on how to protect my devices from ESD. One thing I saw while browsing was TVS Diodes. Reading the literature on these only confused me more. I'm not sure what the highest voltage will develop that I need protection against. I do know my CPLD will be damaged if the the IO pins see more than 4V, so that's the voltage I can tolerate. Other than that, I'm a bit confused and seeking help here.

Any advice on choosing a TVS diode or, heck, another device for ESD Protection?

NOTE: I am aware that a continuity tester may not be enough and I should be measuring resistances. We have a separate machine for that so we're not bothering with including that in this machine.
 
Engineering news on Phys.org
You need to give more info what is the output and what input you are driving to choose.
 
OK, the cable connects to a MOSFET's drain and the other connects to a CPLD's pins. The output high voltage is just 3.3V. To illustrate:

CPLD A's Output -> MOSFET -> Connector -> Wire Under Test -> Connector -> CPLD B's Input

I think there should be ESD protection between CPLD B and the wire.

Is this what you required? The cable's length can be upto 10 meters. Frequency of operation is just 62.5kHz.
 
Last edited:
After some reading, it seems I need determine the peak pulse current. But how do I estimate the voltage that will develop due to ESD? I believe I need to divide that by the impedence of the circuit. Would appreciate any pointers regarding this.
 
saad87 said:
After some reading, it seems I need determine the peak pulse current. But how do I estimate the voltage that will develop due to ESD? I believe I need to divide that by the impedence of the circuit. Would appreciate any pointers regarding this.

You don't need to calculate anything. If your input is only 3.3v get the 3.3v or 4v TVS.

Here is the link to Digikey:

http://search.digikey.com/scripts/DkSearch/dksus.dll

type in TVS, then choose standoff voltage to 3.3v and you have plenty.

TVS has nothing to do with your circuit, all you need to know is you are running 3.3v logic so you find a TVS that has standoff of 3.3v and you are done. The thing you need to be careful is the capacitance of the TVS, you don't want to get a high wattage one and the result is it has so much capacitance that it slow down your circuit. I used a lot of these and I use the smaller SOT package, a dual up and down in one package and I never have problem with it even running at processor speed.

Good luck.
 
Thank you very much, yungman!
 
I had a small question about ESD.

I have implemented TVS diodes on my project at the input side. However, the output is still unprotected. It's a bit like this:

CPLD 1 -> Logic-Level MOSFET -> WIRE UNDER TEST -> TVS DIODE -> Pull up -> CPLD 2.

So the input side is protected from ESD. But the output is still left bare. However, I think they are not needed because if there is a static build up somewhere on the wire, it will be discharged quickly by the TVS diode as it's the quickest path to ground. So it doesn't matter if the output is left unprotected, the TVS diode protects both.

Am I correct in my understanding? Would appreciate some advice.
 
Output is nowhere as sensitive as the input. But if you really want to, you can do it too. I think the CE require this for double failure protection or something. Been a long time.
 

Similar threads

  • · Replies 11 ·
Replies
11
Views
2K
  • · Replies 6 ·
Replies
6
Views
9K
Replies
2
Views
3K
  • · Replies 6 ·
Replies
6
Views
5K
  • · Replies 1 ·
Replies
1
Views
2K
  • · Replies 3 ·
Replies
3
Views
11K
  • · Replies 14 ·
Replies
14
Views
4K
Replies
18
Views
9K
  • · Replies 3 ·
Replies
3
Views
6K
Replies
17
Views
11K