Will this circuit protect my MOSFET from ESD?

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Discussion Overview

The discussion revolves around the effectiveness of a specific circuit design in protecting a MOSFET from electrostatic discharge (ESD). Participants explore the role of a ceramic capacitor in this protection scheme, particularly focusing on its behavior during ESD events and the implications for the MOSFET's gate and source connections.

Discussion Character

  • Exploratory
  • Technical explanation
  • Debate/contested

Main Points Raised

  • One participant expresses concern about whether capacitor C14 can adequately protect the MOSFET from ESD on the source pin, questioning the behavior of internal protection diodes during such events.
  • Another participant suggests that the gate is typically the weakest point and recommends using a transorb for protection rather than relying solely on a capacitor.
  • A different participant mentions that a capacitor can help reduce voltage spikes during ESD events, referencing a specific ESD model.
  • One participant speculates that while C14 may offer some protection, the parallel paths available (Cgs and D12) could still allow enough energy to damage the FET.
  • Another participant argues that the internal ESD diodes of the FET should provide a safe path for current from the source to the gate, as long as the voltage remains below the rated ESD threshold.
  • Concerns are raised about the effectiveness of the capacitor in the context of the discharge duration and its equivalent series inductance (ESL), suggesting that TVS diodes are generally preferred for ESD protection.
  • One participant provides a link to the FET's datasheet and discusses the nature of the discharge event, indicating that the duration will vary based on the charge transfer.

Areas of Agreement / Disagreement

Participants express differing opinions on the adequacy of the capacitor for ESD protection, with some advocating for additional protection measures like transorbs or TVS diodes. The discussion remains unresolved regarding the effectiveness of the proposed circuit design.

Contextual Notes

Participants highlight the importance of considering the capacitor's ESL and the duration of the ESD event, which may affect its protective capabilities. There are also references to specific ESD ratings and behaviors of the MOSFET that are not fully agreed upon.

Who May Find This Useful

Electronics engineers, circuit designers, and students interested in ESD protection strategies for MOSFETs and related components may find this discussion relevant.

¡MR.AWESOME!
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Hey guys and gals. I am curious as to whether this circuit will protect the FET. I am specifically concerned with ceramic capacitor C14. I used the HBM 150pF 330Ohm 25kV with a worst case capacitor bias of 70% (ie: at the ESD voltage, the capacitance will drop to only 30% of it's rated value) to choose the capacitance value. It's an X7R dielectric, btw. The N-MOSFET is this. As you can see, the gate-source junction is protected to 2kV.

I am just curious if C14 will protect the FET from any ESD on the source's pin. I get that the internal protection diodes of the FET will alleviate an ESD event up to 2kV on the GATE, because it will shunt that current to source (which is connected to ground). But what if there is an ESD event on the source pin? Will the current be shunted to the gate or will it just go up through the body diode and out the drain? Either way, is the FET still protected? And what about positive vs negative ESD events?

The gate is ultimately connected to some external voltage. The drain is connected to a Schmitt trigger input (rated to 2kV ESD). The source goes off the board and then is either connected directly to ground or to a switch that will connect it to ground when activated. It will be handled by a human installer, which is why I want ESD protection on it.

Help me out here. I'm not too sure of myself on this one.
 

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Which is the input? I don't even see why the cap is the protection. Usually the gate is the weakest part and you need transorb to protect it. For whatever reason you need to protect the source, you still need transorb, not just a cap.
 
You can use a cap to lower the voltage spike in an ESD event. http://www.tdk.com/pdf/esdmodel.pdf
Btw, D12 is a TVS diode.
 
Last edited by a moderator:
¡MR.AWESOME! said:
I am just curious if C14 will protect the FET from any ESD on the source's pin.

I'll assume the strike occurs on the green net connected to the source and wants to return to ground.

If this is the case then I supposed technically C14 does offer some protection as a fraction of the current will get shunted away by the cap but there is still the parallel Cgs+D12 path and I think any practical discharge will carry enough energy to do damage to the FET.

If the net needs to be protected I recommend using another clamp.
 
Yes, the ESD voltage would be on the green net connected to the source.

Wouldn't the internal ESD diodes (as seen in the datasheet) of the FET provide a path for the current to travel from Source to Gate. As long as the voltage was less than the rated ESD voltage of 2kV, wouldn't it be all good? I'm not trying to argue here, but just to explain my understanding of it.

I calculate that C14 would keep the voltage to ~1,190V.
25kV\frac{150pF}{(150pF+(0.3*10000pF)}=1190V
 
Did you provide a FET data sheet or part number? I am not seeing it for some reason.

I think the duration of the discharge for the HBM is like 0.1uS or something.

I suspect when you add in the ESL of the cap and consider the slew you'll likely find the 10nF cap is not very useful for sinking the strike. This is why TVS diodes are generally used for ESD protection.
 

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