Hey guys and gals. I am curious as to whether this circuit will protect the FET. I am specifically concerned with ceramic capacitor C14. I used the HBM 150pF 330Ohm 25kV with a worst case capacitor bias of 70% (ie: at the ESD voltage, the capacitance will drop to only 30% of it's rated value) to choose the capacitance value. It's an X7R dielectric, btw. The N-MOSFET is this. As you can see, the gate-source junction is protected to 2kV. I am just curious if C14 will protect the FET from any ESD on the source's pin. I get that the internal protection diodes of the FET will alleviate an ESD event up to 2kV on the GATE, because it will shunt that current to source (which is connected to ground). But what if there is an ESD event on the source pin? Will the current be shunted to the gate or will it just go up through the body diode and out the drain? Either way, is the FET still protected? And what about positive vs negative ESD events? The gate is ultimately connected to some external voltage. The drain is connected to a Schmitt trigger input (rated to 2kV ESD). The source goes off the board and then is either connected directly to ground or to a switch that will connect it to ground when activated. It will be handled by a human installer, which is why I want ESD protection on it. Help me out here. I'm not too sure of myself on this one.