s3a
- 819
- 8
- TL;DR
- My understanding:
Pull-up resistor:
* Logic high when switch is open
* Logic low when switch is closed
Pull-down resistor:
* Logic low when switch is open
* Logic high when switch is closed
My goal:
I'm trying to intuit what happens in each arrangement when the switch is on and when it's off.
For the attached image (from https://en.wikipedia.org/wiki/Pull-up_resistor), could someone please help me intuit what happens in each arrangement when the switch is on and when it's off?
So, apparently the pull-up or pull-down resistor is chosen optimally so as to be too low to significantly interfere with the switching device's impedance (as I think can be seen with the voltage divider law), but high enough to prevent a fluctuating voltage when the switch is open.
Also, what is this "to digital input" part exactly? Should I just treat that as a point at which to analyze the potential difference / voltage?
When the switch is closed, is there only one possible logic value for the voltage (assuming proper operation), which would be the opposite of the logical value exhibited when the switch is open or can it be either of the two logic values with the constant and predictable logic value only being the case when the switch is open?
Also, when the switch is open, for both pull-up and pull-down cases, is the reason for the stability because the resistor "pushes" the electrons in the (one) opposite direction, thereby creating certainty?
As you can probably see, I am very confused, so if someone could please help clarify things for me, I would greatly appreciate it!
P.S.
I can also give more information if necessary, so please let me know if you feel something's missing (even if you don't plan to be the one to actually answer my question(s)).
P.P.S.
I included a png version of the svg from Wikipedia for convenience, but the svg is also attached here.
So, apparently the pull-up or pull-down resistor is chosen optimally so as to be too low to significantly interfere with the switching device's impedance (as I think can be seen with the voltage divider law), but high enough to prevent a fluctuating voltage when the switch is open.
Also, what is this "to digital input" part exactly? Should I just treat that as a point at which to analyze the potential difference / voltage?
When the switch is closed, is there only one possible logic value for the voltage (assuming proper operation), which would be the opposite of the logical value exhibited when the switch is open or can it be either of the two logic values with the constant and predictable logic value only being the case when the switch is open?
Also, when the switch is open, for both pull-up and pull-down cases, is the reason for the stability because the resistor "pushes" the electrons in the (one) opposite direction, thereby creating certainty?
As you can probably see, I am very confused, so if someone could please help clarify things for me, I would greatly appreciate it!
P.S.
I can also give more information if necessary, so please let me know if you feel something's missing (even if you don't plan to be the one to actually answer my question(s)).
P.P.S.
I included a png version of the svg from Wikipedia for convenience, but the svg is also attached here.