MHB Implementing f(w1,w2,w3) Using 3-to-8 Binary Decoder & OR Gate

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The discussion focuses on implementing the function f(w1,w2,w3) = Ʃm(0,1,2,4,7) using a 3-to-8 binary decoder and an OR gate. Participants express confusion about circuit concepts like binary decoders and multiplexers (MUX), seeking clarification on definitions and logical operations. There is a request for help in understanding specific solutions provided in external links, particularly regarding the notation used. Additionally, a question is raised about minimizing the expression w1w3' + w2w3' + w1'w2. Overall, the thread highlights the need for clearer explanations of circuit components and logic minimization techniques.
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Show how the function f(w1,w2,w3,) = Ʃm(0,1,2,4,7) can be implemented using a 3-to-8 binary decoder and an OR gate (hint: look at MUX built using a decoder and figure out how to remove the and gates.

Um. Yea. Help.(Speechless)
 
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Well, you've got beyond my personal knowledge of circuits. If there is somebody more knowledgeable on this forum, fine. Otherwise, I am afraid I can't help you with definitions. If you want help, you'll have to provide definitions of new concepts (in this case: binary decoder and MUX) and briefly explain what kind of beast they are. Then I can only help with common mathematical sense.
 
Ok I will see what I can do.
 
so I figured out how to get the function or the output. But Now I don't know hwo they are getting the outupt

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how would i minimize w!w3! + w2w3! + w1!w2
 
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