Interesting video on: Why are 2 logic gates faster than 1?

[eq1]

Just saw an interesting video on youtube explaining Logical Effort very nicely.



https://en.wikipedia.org/wiki/Logical_effort

 

[berkeman]

Can you summarize it please? I'm at work, and can't really watch a video right now... Thanks.

 

[eq1]

The presentation is essentially a summary of this lecture [1], but it's done in a very clear and concise manner, and he uses the OpenRoad ASIC flow [2] with the SkyWater130 PDK [3], which means he can give real world examples.

It starts with an example which is roughly equivalent to slide 22 from lecture 6, but he simulates it, and then he does an example of iterating the front end synthesis of a multiply block, with increasingly tight timing constraints, which is roughly a demonstration of slide 29. But again, it's done with a real flow using a real PDK, which is something one doesn't often see.

[1] http://pages.hmc.edu/harris/cmosvlsi/4e/lect/lect6.pdf
[2] https://github.com/The-OpenROAD-Project/OpenLane/tree/b6f0dc344d83a58f0d28bac1e589fe0295844c69
[3] https://github.com/google/skywater-pdk

 

[berkeman]

Whatever. I'll watch it tonight when I get home.

 

[Baluncore]

Can you summarize it please?

This is an irrational analysis that makes a false claim in the title.
It assumes the one transistor is a logic gate that is charging a huge fixed capacitance with a limited drain current. Or that a two stage amplifier can charge the same huge capacitance faster.
It employs parallel transistors, and confuses the term gate with transistor.
To charge a capacitor faster, more current is needed for a shorter time.
If it confuses you, then analyse it rationally using current sources, charge, energy and capacitors.

 

[eq1]

This is an irrational analysis that makes a false claim in the title.

https://github.com/mattvenn/simulate-gate/blob/inverter-stages/simulation.spice

This is the spice deck he used in the video to demonstrate 2 and 3 gates in series are faster than 1, can you kindly point out the error?

It's following the same steps in the example in the lecture from Weste and Harris's text. (http://pages.hmc.edu/harris/cmosvlsi/4e/index.html) That example, which starts on slide 22 in the deck I linked, shows (on slide 29) for the register file given (data path load = 16) the path with two gates in series (row 2) is faster than the path with one gate (row 1). So which claim is the false one?

In fact, the path with 4 gates in series (row 7) was the faster one.

It employs parallel transistors, and confuses the term gate with transistor.
To charge a capacitor faster, more current is needed for a shorter time.

Umm... parallel transistors leads to more current, no? Since we have more current, it will charge the same capacitor faster.

This can be true even with a logical fanout of 1, so ignore the big cap at the end. Different gates will have different input and output capacitances as well as different drive strengths. Managing these trade-offs can lead to cases were multiple gates in series are faster than 1 even though they implement the same boolean equation, and this is exactly what the yosys tool (via the synthesizer ABC) is doing at timestamp 7:50.

 

[Baluncore]

So which claim is the false one?

It is a false claim that two "logic gates" in series are faster than one. That is only true when the logic gates are being misused as power amplifiers, driving capacitive loads, which makes it an impedance transformer, not a logic gate. An inverter is not really a "logic gate" as it is not combinatorial logic.

Two gates in parallel are faster than one, which is what is being done by using many parallel transistors in the second stage of the amplifier, wrongly termed a "gate".

One does not use a logic gate to drive a large capacitive load. To do that one uses an array of parallel of transistors. The number of stages of amplification determines the total delay time, area and power.

Umm... parallel transistors leads to more current, no?

I don't understand. Are you agreeing with me, or questioning if the addition of parallel drain currents should be added ?

You appear to be lost in the detail, and the misuse of the term "logic gate".

 

[DaveE]

This is so much simpler than it appears, at least IMO. His gates aren't the same. The first gate is small and has an easily driven input. Then the gain from that drives the next stage which is big and can drive his bigger (low impedance) load. He seems to think inverters are always made from 2 fets, I guess.

I would retitle this as "Why most good amplifiers (or gates) have separate input and output stages."

 

[eq1]

It is a false claim that two "logic gates" in series are faster than one.

That must mean this spice deck has an error.
https://github.com/mattvenn/simulate-gate/blob/inverter-stages/simulation.spice

It clearly shows signal Y3_16 arriving before Y1_1. Can you please point out the error?

 

[DaveE]

Also, it didn't inspire a lot of confidence when he said he thought CMOS supply current was from shoot-thru currents and was surprised to learn that the gate charge currents were significant too.

CMOS is ALL ABOUT gate capacitance, it's like the only thing that matters.

 

[Baluncore]

That must mean this spice deck has an error. It clearly shows signal Y3_16 arriving before Y1_1. Can you please point out the error?

You are easily lead by the nose.
A "two stage power amplifier" is not "two logic gates in series".

 

[Baluncore]

Also, it didn't inspire a lot of confidence when he said he thought CMOS supply current was from shoot-thru currents and was surprised to learn that the gate charge currents were significant too.

That is what got me to question his logic. He is a neophyte.

 

[eq1]

He seems to think inverters are always made from 2 fets, I guess.

I get the impression you all didn't actually watch the video, which is fine. But I think it's unfair to make these claims in that case.

In the video at timestamp 2:50 he shows the layout of inv4 and then inv16 and he clearly shows there are multiple transistors so he's obviously aware some gates are made from more than 2 FETs.

 

[Baluncore]

I get the impression you all didn't actually watch the video, which is fine.

I watched it and it was a waste of time.
I understand the mistakes he is making, and recognise my mistake at being hooked by the title of the video you posted, that is now wasting more of our time.
You need a better crap detector.

 

[eq1]

You are easily lead by the nose.
A "two stage power amplifier" is not "two logic gates in series".

Ummm... what? Who is talking about amplifiers?

I'll copy/paste part of the deck for you. Where are the amplifiers?

* 1 inverter
X1_1 A_1 VGND VGND VPWR VPWR Y1_1 sky130_fd_sc_hd__inv_1
C1 Y1_1 VGND 0.1pF

* 2 inverters
X2_1 A_2 VGND VGND VPWR VPWR Y2_1 sky130_fd_sc_hd__inv_1
X2_8 Y2_1 VGND VGND VPWR VPWR Y2_8 sky130_fd_sc_hd__inv_8
C2 Y2_8 VGND 0.1pF

* 3 inverters
X3_1 A_3 VGND VGND VPWR VPWR Y3_1 sky130_fd_sc_hd__inv_1
X3_4 Y3_1 VGND VGND VPWR VPWR Y3_4 sky130_fd_sc_hd__inv_4
X3_16 Y3_4 VGND VGND VPWR VPWR Y3_16 sky130_fd_sc_hd__inv_16
C3 Y3_16 VGND 0.1pF

 

[eq1]

I understand the mistakes he is making

Thank you for letting us know. I'll email the SkyWater Foundry and tell them they are wasting their time on all the gate variants in the PDK. They will be happy to hear that because it's going to save them a lot of time.

 

[Baluncore]

They will be happy to hear that because it's going to save them a lot of time.

No, they will not be happy as this is all part of their misleading advertising.
They have hooked you as their free agent, and you are failing.

Ummm... what? Who is talking about amplifiers?

YOU ARE.
The first "logic gate" is a pre-amplifier stage.
The second "logic gate" is the output stage of a power amplifier.

 

[DaveE]

Who is talking about amplifiers?

Gates are amplifiers, amplifiers are gates. Yes, they are optimized for different applications. But most of the key concepts are the same. My advice, grasshopper, leave the SPICE alone for a while and read a good textbook about transistor amplifiers.

 

[DaveE]

Thank you for letting us know. I'll email the SkyWater Foundry and tell them they are wasting their time on all the gate variants in the PDK. They will be happy to hear that because it's going to save them a lot of time.

Sorry you aren't liking our answers. Perhaps you should just stick with the answers you wanted to hear? I'll go away now.

 

[berkeman]

Okay, I'm home now and will watch the video soon. For now the thread is locked.

 

[berkeman]

It is a false claim that two "logic gates" in series are faster than one. That is only true when the logic gates are being misused as power amplifiers, driving capacitive loads, which makes it an impedance transformer, not a logic gate. An inverter is not really a "logic gate" as it is not combinatorial logic.

I watched it and it was a waste of time.

Agreed. If he submitted this along with his resume in a job application to me and my company, his job application would be rejected.

He obviously has no real experience in designing CMOS ICs, and is just playing around with tools and guessing at stuff. You don't drive a large fan-out with one gate, no matter how many parallel transistors you stack at the output. You use a structure like a clock tree instead. If you have a high capacitance load, you use an amplifier stage like @Baluncore said.

I'm not going to change the thread title and reopen it. @eq1 -- if you want to open a new thread to talk about real digital CMOS IC design and timing, please do that with a better reference than a clumsy YouTube video from an amatuer.