Quick questions about logic gates (Nand, nor, etc)

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So recently just in my spare times i've found an interest in logic gates such as the nand gates and nor gates and such and although most of it's logic, there's one thing i just couldn't figure out.

Let's say you have a nand gate configuration consisting of two pmos and two nmos transistors as in my attached picture, what exactly is the purpose of the two nmos transistors at the bottom? I'm guessing it's related to removing any voltage on the output as soon as A and B go high.

Another question I have though; Why is usually pmos transistors used at the top? If i'm not entirely mistaken, aren't nmos transistors supposed to be faster? Or is this to avoid a voltage drop when your A or B signals are high?

And finally thirdly, would it be possible to create a transistor with two seperate gate elements in which both needs to be set high in order to allow for current to go through? A single-transistor and-gate in other words.

Thanks for any input on this! been scratching my head.
 

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