I haven't done any Bode plots before, and so I'm reading about LDO stability and I came across this file, which I am trying to understand:(adsbygoogle = window.adsbygoogle || []).push({});

http://www.ti.com/lit/an/slyt194/slyt194.pdf

Under the stability analysis, it names the poles and zeroes. How are these calculated? I assume that the circuit is cut open at some point (at the + input of the error amplifier?) and the transfer function from one open end to the other is calculated?

For the first pole, if I put a small signal at the + input of the error amplifier, then I take the transistor to be a variable resistor, so the signal will vary the resistance. Instead of a varying the resistance I take that the V_IN signal varies (it should have the same result, assuming that the variations are small).

So with a varying V_IN and taking that all the other resistances are big compared to the output capacitor (the R_ESR and C_LOAD in the figure in the pdf), I get (using impedances) that the V_OUT change is proportional to:

$$\frac{R_{ESR}+\frac{1}{i\omega C_{LOAD}}}{R_{CMOS}+R_{ESR}+\frac{1}{i\omega C_{LOAD}}} \propto

\frac{i\omega + \frac{1}{R_{ESR}C_{LOAD}}}{i\omega + \frac{1}{(R_{CMOS}+R_{ESR})C_{LOAD}}}$$

Basically I reduced the system to a series connection of R_CMOS, C_LOAD and R_ESR. So this seems to be where the first pole comes from that they mention in the pdf, and also the zero.

Using similar reasoning I can understand where the third pole comes from. But where does the second pole come from, the one with ##\omega = 1/(R_{ESR}C_{BP})##?

Also looking at figure 3 for example, shouldn't the zero fz1 at 1.59 MHz cause the phase to increase by 90 degrees?

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# LDO voltage regulator stability

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