# LDO voltage regulator stability

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1. Dec 17, 2016

### chingel

I haven't done any Bode plots before, and so I'm reading about LDO stability and I came across this file, which I am trying to understand:

http://www.ti.com/lit/an/slyt194/slyt194.pdf

Under the stability analysis, it names the poles and zeroes. How are these calculated? I assume that the circuit is cut open at some point (at the + input of the error amplifier?) and the transfer function from one open end to the other is calculated?

For the first pole, if I put a small signal at the + input of the error amplifier, then I take the transistor to be a variable resistor, so the signal will vary the resistance. Instead of a varying the resistance I take that the V_IN signal varies (it should have the same result, assuming that the variations are small).

So with a varying V_IN and taking that all the other resistances are big compared to the output capacitor (the R_ESR and C_LOAD in the figure in the pdf), I get (using impedances) that the V_OUT change is proportional to:

$$\frac{R_{ESR}+\frac{1}{i\omega C_{LOAD}}}{R_{CMOS}+R_{ESR}+\frac{1}{i\omega C_{LOAD}}} \propto \frac{i\omega + \frac{1}{R_{ESR}C_{LOAD}}}{i\omega + \frac{1}{(R_{CMOS}+R_{ESR})C_{LOAD}}}$$

Basically I reduced the system to a series connection of R_CMOS, C_LOAD and R_ESR. So this seems to be where the first pole comes from that they mention in the pdf, and also the zero.

Using similar reasoning I can understand where the third pole comes from. But where does the second pole come from, the one with $\omega = 1/(R_{ESR}C_{BP})$?

Also looking at figure 3 for example, shouldn't the zero fz1 at 1.59 MHz cause the phase to increase by 90 degrees?

Last edited: Dec 17, 2016
2. Dec 18, 2016

### analogdesign

Hi Chingel,

You're on the right track with calculating the poles and zeros. In practice, it is usually simpler to just look at the nodes, calculate the resistance and capacitance at each one and there are your poles. An LDO is simpler than most circuits for doing it because it is mostly unilateral.

I second pole comes from the technique I mentioned. Look at the top of Resr. What cap does it see? Well, Cload is large and in series so its impedance = 1/sC will be very small so it looks like a short circuit. A low impedance to GROUND though makes a pole and that is what CBP is.

As for figure 3, the zero is in the right half plane of the pole-zero diagram so it worsens the phase response in a similar way that the zero generated by the compensation cap worsens the phase response in a Miller op amp.

3. Dec 19, 2016

### chingel

I see, the second pole comes because at some frequency you need to neglect C_LOAD and the C_BP plays the important role in the impedance. In contrast to the first one, where we ignored C_BP and considered C_LOAD.

What do you mean that the zero is in the right half plane? Is the zero I calculated correct? If $\omega$ is very big then the numerator is roughly $i\omega$ and it causes a 90 degree shift?

If we would have $-i\omega + \frac{1}{R_{ESR}C_{LOAD}}$ instead of $i\omega + \frac{1}{R_{ESR}C_{LOAD}}$ then it would contribute to the phase shift in the same direction as the denominator?

4. Dec 20, 2016

### analogdesign

I meant right half plane as in the zero position is in the right half plane in the Laplace domain. The hand-wavy engineer's answer is that the zero is in the right half plane because the zero shorts the about and lets the signal through without phase shift. I much more theoretical explanation you might like is here: http://www.edaboard.com/thread155316.html

You can find the math in any analog design textbook. Look up Miller opamp or Two-Stage Op amp.