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Need a layout/map on what to learn to acheive the following project

  1. May 24, 2007 #1
    Hey there...

    I am a second year EE student and I have always been interested in knowing FPGA,ASIC,HDl's....etc but I never had a chance to sit down and start learning them.Fortunately a design contest has been prepared for college students by a very well known company in EDA and I want to join this contest but I need to know what I should start learning and where can I get learning resources.This is the description of the project.Thanks in advance


    Automotive Bus Analyzer and Emulator (ABAE)


    This project aims at developing a hardware FPGA based bus analyzer and emulator. This will enable the user to monitor frames on the automotive bus and will enable him to send frames and emulate certain scenarios. Typical automotive buses are CAN, LIN and Flexray. The analyzer will monitor and inject frames in an on-line interaction with different electronic control unit (ECU) on bus. It’s also required to build higher PC interface

    Project Description:

    The ABAE is a System-on-Chip that communicates with an automotive bus. Implementing CAN, LIN, and Flexray controllers, is a necessary step. Having a microcontroller core and necessary peripherals is also a basic building block. The ABAE will also communicate with the high-level software through a serial interface. This project consists of design, implementation and testing the ABAE with a real automotive bus with required topology.

    Product Features:
    • Hardware implementation of CAN controller.
    • Hardware implementation of LIN controller.
    • Hardware implementation of Flexray controller.
    • Integration with relevant transceivers.
    • Reuse/development of different required open-cores
    • Hardware implemented USB interface.
    • High-level software enabling the user to:
    a. Receive/receive different types of frames.
    b. Emulate bit/frame level errors on bus
    c. Execute higher level automation scripts
  2. jcsd
  3. May 25, 2007 #2


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    Staff: Mentor

    That sounds like an excellent (and very real world) project! It also sounds like a bit much for a 2nd year EE student, but I definitely encourage you to use it as motivation for learning more about developing projects that involve uC and CPLD/FPGA building blocks.

    One of the best first steps is to download the free WebPack FPGA design software from Xilinx, and the QuartusII design software from Altera:



    The Xilinx package especially is really amazing in its capability, considering that it is available free.

    Then I would suggest starting out by taking just one portion of the design contest project, and learning how to design an FPGA for that portion. In addition to the design software, Xilinx has a large amount of tutorial information on their website.

    Does your school offer any kind of CPLD/FPGA classes with labs?
  4. May 25, 2007 #3
    Unfortunately not.But I can probably convince my TA's and Professors to teach me FPGA's.But the problem is that I need to know what to learn first cause I have zero knowledge in this field
  5. May 25, 2007 #4


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    Staff: Mentor

    Have you learned about state machines and logic design yet? That's basically what CPLD and FPGA designs are -- implementing the state machines, MUXes and other logic, along with the IOs out to the external circuitry. The best place to start is with PALs -- you can even get them in DIP packages to make them easy to prototype with. The 22V10 is an example of a jellybean PAL.

    Xilinx has a neat little book, "Introduction to Programmable Logic" that comes with some of their design kits (I think that's where I got it). A condensed text version is here:


    Ooo, and I found this nifty book at the Xilinx website as well:


    So I'd recommend starting with the QuartusII software and desiging a couple PAL/CPLD projects -- just simple stuff like a traffic light controller or elevator controller or something. Those are nice too, because since you are interfacing with sensors that can give you a signal at any time (asynchronous to your CPLD system clock), you need to learn about synchronizing input signals to your system clock, which is VERY important in real-world designs.

    You can initially start coding your PAL/CPLD/FPGA projects in HDL (hardware design language), which is pretty intuitive and easy to learn. Later, though, you should start using Verilog/RTL (what is used in Silicon Valley the most), or VHDL (which is popular elsewhere, and probably easier to learn).

    If you can also interest a few other students to go down this learning path with you, then by your senior year, you should be able to organize a team to compete in the EDA competition. You will need a project manager, and you will need to divide up the tasks and make sure that the whold team stays synchronized (no pun intended) and productive and creative.

    Best of luck!
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