Node Voltage: Where to choose ground?

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SUMMARY

The discussion centers on the implications of swapping ground and Node C in a circuit analysis context. Participants emphasize the importance of correctly applying Kirchhoff's Voltage Law (KVL) and maintaining accurate signs for voltage sources in node equations. Specifically, the expression for current i1 is derived as i1 = (VC + 125 - VA) / 1, highlighting the necessity of understanding potential changes during KVL walks. The conversation concludes that nodal analysis requires precise sign usage, as opposed to the "first sign encountered" method, which may lead to errors in calculations.

PREREQUISITES
  • Understanding of Kirchhoff's Voltage Law (KVL)
  • Familiarity with nodal analysis techniques
  • Knowledge of circuit components such as voltage sources and resistors
  • Ability to interpret and manipulate circuit equations
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  • Study advanced nodal analysis techniques in electrical engineering
  • Learn about Kirchhoff's Laws in greater detail
  • Explore the implications of ground reference points in circuit design
  • Practice solving circuit problems using KVL with varying configurations
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Electrical engineering students, circuit designers, and anyone involved in circuit analysis and troubleshooting will benefit from this discussion.

rugerts
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Homework Statement
Find the branch currents.
Relevant Equations
KCL and Ohm's -> Node Voltage
Hello,
Here's the example I'm looking at now.
1573416908834.png

I am wondering if I swap ground and Node C... will this still be correct? I can see how it's more useful to have ground where it is above, but I'd still like to know if it would work for a swap of C and GND.

Here's my work trying this:
1573416988769.png

Does anyone see where I went wrong?
 
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Check the signs you've used for the voltage sources in your node equations. Also, I see that node B involves currents i2, i4, and i5, but not i3.
 
gneill said:
Check the signs you've used for the voltage sources in your node equations. Also, I see that node B involves currents i2, i4, and i5, but not i3.
Why should it involve i3?

And, for the signs, it feels like there's something wrong with the Vc - 125 - Va part since, if GND were in C's spot, i1 would = 125- Va. Could you provide any clues as to what's going on here?
 
rugerts said:
Why should it involve i3?
It should not. In your work you wrote for node B:
1573420599079.png


And, for the signs, it feels like there's something wrong with the Vc - 125 - Va part since, if GND were in C's spot, i1 would = 125- Va. Could you provide any clues as to what's going on here?
Let's examine the expression for the ##i_1## branch. If you do a "KVL walk" from node C to node node A then your starting potential is ##V_C##, then you "walk" through the 125 V supply increasing your potential to ##V_C + 125##. Next you pass through the resistor, dropping your potential to reach ##V_A##. Hence the expression for ##i_1## is:

##i_1 = \frac{V_C + 125 - V_A}{1}##
 
gneill said:
It should not. In your work you wrote for node B:
View attachment 252668Let's examine the expression for the ##i_1## branch. If you do a "KVL walk" from node C to node node A then your starting potential is ##V_C##, then you "walk" through the 125 V supply increasing your potential to ##V_C + 125##. Next you pass through the resistor, dropping your potential to reach ##V_A##. Hence the expression for ##i_1## is:

##i_1 = \frac{V_C + 125 - V_A}{1}##
Interesting. What you say for the KVL walk makes sense, but I had thought that for KVL walks you simply write down the first sign you encounter. Here, for a clockwise loop, I hit the minus terminal first, which results in -125 instead of +125. What is the flaw in this "first sign you encounter" approach? I've definitely heard my prof. mention this method for KVL walks along with another (which is most likely the one you mention).
 
I've never used your "first sign encountered" rule before. I've always just done the KVL walk in the direction of assumed loop (or branch) current when those current directions are specified in the problem statement.

Otherwise, if they are not given, I just assume that all currents at a given node are flowing out of the node in question and that they sum to zero. The math takes automatically takes care of sorting out the signs (hence directions) of the actual currents.

To me it makes sense that the potential at the left end of the resistor in that branch must be ##V_C + 125##

1573426147836.png
 
gneill said:
I've never used your "first sign encountered" rule before. I've always just done the KVL walk in the direction of assumed loop (or branch) current when those current directions are specified in the problem statement.

Otherwise, if they are not given, I just assume that all currents at a given node are flowing out of the node in question and that they sum to zero. The math takes automatically takes care of sorting out the signs (hence directions) of the actual currents.

To me it makes sense that the potential at the left end of the resistor in that branch must be ##V_C + 125##

View attachment 252672
1573426566807.png

Here's a screenshot of the relevant slide.
What you say of course works and makes sense. It's just strange the other alternative doesn't work here. Do you think that alternative way may not apply here because we're working with node voltages, and the node voltage doesn't have a sign component to it? That is, there aren't any terminals (and hence no signs to go off of) to work with for Vc. Vc is just the sum of the voltages on its branch.
 
Thanks for the screenshot.

I suspect that the reason the method works for KVL full loops is that the summation of potential changes is set equal to zero regardless of whether you are summing potential rises or potential drops (multiply through by -1 and the equation remains valid).

When you're doing nodal analysis you're not doing the summation over a closed loop but just along a branch, so using the "correct" signs for potential changes along the walk matters.
 
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