Positive-Edge-Triggered JK flip-flops

  1. Hi guys,

    I'm simulating a circuit which uses a few (actually, 10) Positive-Edge-Triggered JK flip flops.

    The exact flip-flop design that I'm using is the SN7476 from TI. I need a flip-flop like this, since I need Preset and Clear asynchronous inputs. The datasheet is as follows:
    http://www.ti.com/lit/ds/symlink/sn7476.pdf

    In fact, as I'm simulating a circuit with MOS only transistors, I found an adaptation for this circuit on the following link:
    http://tams-www.informatik.uni-hamb...16-flipflops/40-jkff/SN7476-single_print.html which simplifies my circuit a little bit.

    As I use it for simulation, I'd like to use a simpler version of this flip-flop, to speed up the process (at this moment, my focus is not the design, I just need to make things faster.)

    Is there an alternative for this circuit which uses a lower number of transistors?
    I know this is an Master/Slave flip-flop. I tried to inplement an equivalent circuit using this topology: http://2.bp.blogspot.com/-fxhp4O9oDEo/UGH4G6SSF8I/AAAAAAAAAJ0/ueUKXx0-Eew/s1600/jkffcirc.gif as well as this one http://wearcam.org/ece385/lectureflipflops/flipflops/fig6a.gif with the additional preset/clear signals, but it didn't work as expected.

    Is there any equivalent popular IC to SN7476? I know that SN7476 is "obsolete", so I took a look at NXP's 74LVC109, but the number of gates goes beyond what I need right now.

    Any ideas?
    Thank you in advance.
     
  2. jcsd
  3. Is there a reason you're using JK flip-flops? You can do anything with a D flip-flop and it is much simpler.
     
  4. Not sure why you chose JK. Not sure how fast you want to go. There are lots of 7474 equivalent D flops with set and reset on each flop.

    High Speed CMOS 74AC74 (125MHz @ 5V)

    There are different technologies, like ECL and SIGe that go to the GHz.
     
  5. It's an old design for a control logic of an ADC. It was proposed on 1972. They proposed a version using D flip flops, which uses 2N+2 DFFs and a version with JK with N+1 FFs. Of course it was targeted to LSI/MSI applications.

    I did some calculations, and found out that the JK version requires 540 transistors (using the 7476 topology), while the D version requires 648 (using 7474). My simulations show that, because of this, the JK version is much faster.
    These simulations take a lot of time. My goal right now is to speed up the process a little bit more...

    The point is: I don't care exactly about the flip-flop type right now, but the number of transistors they use...

    Thank you.
     
  6. Like I said before (in other words), the good old 7474 ( http://home.gwi.net/~pstewart/7474diag.gif ) uses 6 nand3 gates (which in cmos would require 36 transistors).

    For the design I'm using, despite the higher number of transistors/flip-flop, it's still a better trade-off in terms of transistor count.

    But thank you for your suggestion.
     
  7. Last edited: May 13, 2014
  8. Not building exactly, just designing. I'm free to use custom flip-flops. I just used the ones that the paper suggested.

    Take a look at: http://ipnpr.jpl.nasa.gov/progress_report2/XIII/XIIIW.PDF
    p. 5 shows the classical approach with D flip flops and p. 9 shows the alternative one with JK FFs
     
  9. BTW, You can add transistors (logic) to the basic 10 transistor D flop to get JK functionality. I'll let you play with that.
     
  10. Wow, that's really impressive. I'll see if it works.

    Yeah, The point here is that I don't care about the FF design right now, I just need it to be as fast as possible for characterization purposes.

    Thank you.
     
  11. Last edited: May 13, 2014
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