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Regarding jk flip flop Q' stability.

  1. Dec 17, 2011 #1

    I am trying to understand and analyze JK flip flop's (using RS flop flop i.e. using NOR gates). I have written out the characteristic table and when I give Q = 1, J=1 and K = 0 I am trying to analyze the Q' (Q complement) by giving the intial state to 0. I find that Q settles to 1 (i.e. Q(t+1)) but Q' oscillates between 0 and 1. How is this fixed? Is the Q' needed in JK flip flops? Also why do textbooks don't talk about Q' in JK or D or T but only Q and Q(t+1) ?

  2. jcsd
  3. Dec 31, 2011 #2

    No it wont oscillate for Q=1, J=1, K=0. AND gate with i/p K will always be 0 and AND gate with i/p Q' will always be 0, making FF to hold its state.

    However, for J=1, K=1, If the clock enable time is larger than Q/Q' to R/S delay the circuit will oscillate. To resolve the problem use master slave JK FF.
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