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Engineering and Comp Sci Homework Help
Problem involving timing diagram with delays
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[QUOTE="s3a, post: 6008045, member: 235803"] [h2]Homework Statement [/h2] Problem statement: https://www.docdroid.net/FwEvlgl/question4-problemstatement.pdf [ATTACH=full]226611[/ATTACH] Provided solution: https://www.docdroid.net/1MkmPKT/question4-solution.pdf [ATTACH=full]226612[/ATTACH] [h2]Homework Equations[/h2] NOT Gate OR Gate Timing Diagram Delays [h2]The Attempt at a Solution[/h2] The part for x is just "normal" because there are no delays. The part for x' takes 2 ns to respond to the first "cutoff time" (t = 10 ns) and then takes 2 ns to respond to the second "cutoff time" (t = 20 ns) and then again takes 2 ns to respond to the fourth/last "cutoff time" (t = 40 ns). At the second "cutoff time", F is 0 + 0 = 0, but takes 4 ns to reflect that, but then, AND THIS IS THE PART I'M HAVING TROUBLE WITH, what's with the 2 on the line for F? Also, especially for the part with the 2 on the F line, is it just not drawn to "pseudo-scale"? (I ask because it seems to be visually implying that 4 ns + 2 ns ≈ 10 ns.) Could someone please help me understand what's going on there? Any input would be GREATLY appreciated! [/QUOTE]
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Engineering and Comp Sci Homework Help
Problem involving timing diagram with delays
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