Problem involving timing diagram with delays

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In summary, the problem is that the graph is not drawn to pseudo-scale, and the problem with the F line is that it is not drawn to pseudo-scale and it is confusing because the 4 ns is a propagation delay and the 2 ns isn't here. The max speed of this circuit is 166.6MHz.
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Homework Statement


Problem statement:
https://www.docdroid.net/FwEvlgl/question4-problemstatement.pdf
upload_2018-6-4_9-50-24.png

Provided solution:
https://www.docdroid.net/1MkmPKT/question4-solution.pdf
upload_2018-6-4_9-51-5.png

Homework Equations


NOT Gate
OR Gate
Timing Diagram
Delays

The Attempt at a Solution


The part for x is just "normal" because there are no delays.

The part for x' takes 2 ns to respond to the first "cutoff time" (t = 10 ns) and then takes 2 ns to respond to the second "cutoff time" (t = 20 ns) and then again takes 2 ns to respond to the fourth/last "cutoff time" (t = 40 ns).

At the second "cutoff time", F is 0 + 0 = 0, but takes 4 ns to reflect that, but then, AND THIS IS THE PART I'M HAVING TROUBLE WITH, what's with the 2 on the line for F? Also, especially for the part with the 2 on the F line, is it just not drawn to "pseudo-scale"? (I ask because it seems to be visually implying that 4 ns + 2 ns ≈ 10 ns.)

Could someone please help me understand what's going on there?

Any input would be GREATLY appreciated!
 

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  • #2
I think the 2 ns on the F line is the duration of the 0 pulse. This is confusing, because the 4 ns is a propagation delay and the 2 ns isn't here. (Though of course it derives from an earlier pd.) I like to show the pd's with a sloping arrow from the triggering event to the change it causes, but durations as horizontal arrows.

I agree the scale is not very good, but as long as you get the qualitative features right, you can just label the delays or timings. It doesn't matter whether it is accurately drawn. It would be nice to have some gap at the end of the pulse before to 10 ns marker.

I found it helpful to draw in (X or X') without any 4 ns delay, then delay this 4 ns to give F.

I'd have thought the graph should have been extended further to the right to show the second pulse.
 
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  • #3
Contamination delay is?
Propergation delay is?

I don't want to give the answer but I am sure you'll figure it out. But I will tell you this, the max speed of this circuit is 166.6MHz.
 
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  • #4
Interesting. I'd not come across this concept before (tcd.) I'll need to study it a bit to understand how it can be used.

I'm not sure how you reach the 166 MHz. I can see this gives the time between pulses of 6 ns, which is tpd along the critical path.
But I'm not sure why the circuit can't just output the 2 ns pulses with a delay of 6 ns (or more), until X is approaching 250 MHz.
The start of the F pulse seems to follow the falling X and the end of the F pulse follows the falling X delayed by the inverter. This sets the F pulse duration at the propagation delay of the inverter - somewhere between tcd and tpd for that inverter. This pulse is delayed by the propagation delay of the OR gate.

The limiting factor looks like having a second falling X before the Q has changed from the previous falling X - which will happen if Tx <= 2 ns, or Fx >=500 MHz.
At 500 MHz, there is no F output. Upto 250 MHz the output pulses are 2 ns, but from there up to 500 MHz,the output pulses reduce in width, because they are terminated by the rising X after T/2 rather than the rising Q after the 2 ns tpd.

In these diagrams, Q is the output of the inverter and F is a delayed copy of Q OR X.
gate_timing4.png
 

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  • #5
I think that the lines for ##\bar x## and ##F## were just drawn too long in that section. The length of the 2 ms for ##\bar x## is longer than it should be. It should have only been 1/5 th of that time section. Likewise the 4 ms for ##F## is longer than it should be.
 

Related to Problem involving timing diagram with delays

1. What is a timing diagram with delays?

A timing diagram with delays is a graphical representation of the sequence of events in a system or process, including the delays between each event. It is commonly used in engineering and computer science to analyze the timing and performance of a system.

2. How is a timing diagram with delays created?

A timing diagram with delays is typically created using specialized software or by hand-drawing on graph paper. The diagram consists of horizontal lines representing signals or events, and vertical lines representing time. Delays are indicated by gaps or overlapping lines in the diagram.

3. What is the purpose of using a timing diagram with delays?

The main purpose of a timing diagram with delays is to analyze and optimize the timing and performance of a system. It can help identify potential issues or bottlenecks, and ensure that all events occur in the correct sequence. It is also useful for communicating the timing requirements of a system to other team members or stakeholders.

4. How are delays represented in a timing diagram?

Delays are represented in a timing diagram by gaps or overlapping lines between the events. The length of the gap or overlap represents the length of the delay, and is typically labeled with a time value. Some diagrams may also use arrows or other symbols to indicate the direction of the delay.

5. What are some common challenges when using a timing diagram with delays?

Some common challenges when using a timing diagram with delays include accurately measuring and representing the delays, ensuring that all events are accounted for, and understanding the impact of delays on the overall performance of the system. It is important to carefully plan and validate the diagram to ensure its accuracy and usefulness.

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