# Problem involving timing diagram with delays

## Homework Statement

Problem statement:
https://www.docdroid.net/FwEvlgl/question4-problemstatement.pdf

Provided solution:
https://www.docdroid.net/1MkmPKT/question4-solution.pdf

NOT Gate
OR Gate
Timing Diagram
Delays

## The Attempt at a Solution

The part for x is just "normal" because there are no delays.

The part for x' takes 2 ns to respond to the first "cutoff time" (t = 10 ns) and then takes 2 ns to respond to the second "cutoff time" (t = 20 ns) and then again takes 2 ns to respond to the fourth/last "cutoff time" (t = 40 ns).

At the second "cutoff time", F is 0 + 0 = 0, but takes 4 ns to reflect that, but then, AND THIS IS THE PART I'M HAVING TROUBLE WITH, what's with the 2 on the line for F? Also, especially for the part with the 2 on the F line, is it just not drawn to "pseudo-scale"? (I ask because it seems to be visually implying that 4 ns + 2 ns ≈ 10 ns.)

Any input would be GREATLY appreciated!

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Merlin3189
Homework Helper
Gold Member
I think the 2 ns on the F line is the duration of the 0 pulse. This is confusing, because the 4 ns is a propagation delay and the 2 ns isn't here. (Though of course it derives from an earlier pd.) I like to show the pd's with a sloping arrow from the triggering event to the change it causes, but durations as horizontal arrows.

I agree the scale is not very good, but as long as you get the qualitative features right, you can just label the delays or timings. It doesn't matter whether it is accurately drawn. It would be nice to have some gap at the end of the pulse before to 10 ns marker.

I found it helpful to draw in (X or X') without any 4 ns delay, then delay this 4 ns to give F.

I'd have thought the graph should have been extended further to the right to show the second pulse.

FactChecker
Contamination delay is?
Propergation delay is?

I don't want to give the answer but Im sure you'll figure it out. But I will tell you this, the max speed of this circuit is 166.6MHz.

Last edited:
Merlin3189
Merlin3189
Homework Helper
Gold Member
Interesting. I'd not come across this concept before (tcd.) I'll need to study it a bit to understand how it can be used.

I'm not sure how you reach the 166 MHz. I can see this gives the time between pulses of 6 ns, which is tpd along the critical path.
But I'm not sure why the circuit can't just output the 2 ns pulses with a delay of 6 ns (or more), until X is approaching 250 MHz.
The start of the F pulse seems to follow the falling X and the end of the F pulse follows the falling X delayed by the inverter. This sets the F pulse duration at the propagation delay of the inverter - somewhere between tcd and tpd for that inverter. This pulse is delayed by the propagation delay of the OR gate.

The limiting factor looks like having a second falling X before the Q has changed from the previous falling X - which will happen if Tx <= 2 ns, or Fx >=500 MHz.
At 500 MHz, there is no F output. Upto 250 MHz the output pulses are 2 ns, but from there up to 500 MHz,the output pulses reduce in width, because they are terminated by the rising X after T/2 rather than the rising Q after the 2 ns tpd.

In these diagrams, Q is the output of the inverter and F is a delayed copy of Q OR X.

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