Problems building a 1 bit / 2 to 1 Multiplexer

[Avencherus]

First let me just I'm a total newbie to electronics, but I would like to progressively learn how computers work by building the little components with the small parts, and then work up to the ICs once I understand how to make rudimentary versions.

I'm trying to make a 1-bit multiplexer out of transistors and resistors, maybe I need more components than that. I'm not 100% clear on the resistance values I need for a 9V battery and bread board either.

Was wondering if anyone could give me some pointers. I've attached a schematic I've come up with to try and implement those ANDs and NOT to create a 2 to 1 selector.

I'm suspecting that maybe the ground is just draining the circuit here, but my troubleshooting skills here are in their infancy as well. I don't know how to confirm it or what I have to do to make it behave in the intended way.

Thanks to anyone who has any pointers or resources.

 

[mfb]

I've attached a schematic I've come up with to try and implement those ANDs and NOT to create a 2 to 1 selector.

Did you design the multiplexer on that level?
Do that first, then plug in the transistors and resistors later.

 

[Avencherus]

Did you design the multiplexer on that level?
Do that first, then plug in the transistors and resistors later.

Yeah, now I'm trying to actually build the physical thing out of the abstraction. I did go back and look at my drawings and I realized that I created that graphic wrong there above. Let me update that. I had an AND instead of an OR at the end.

And the abstract diagram as well. Hopefully I didn't whip that one together too hastily. X)

I would say my problem is taking these logic gate diagrams and converting them into functional schematics you can build with a bread board and components.

 

[mfb]

There are some more cable bridges needed. Currently you connect B to plus, for example. The output seems to be coupled with something close to B, while one transistor has an open connection. Your "NOT sel" seems to do nothing apart from connecting plus and minus via a transistor.

It would help if you separate the different components better, and mark them in the sketch of the transistor/resistor layout.

 

[Avencherus]

There are some more cable bridges needed. Currently you connect B to plus, for example. The output seems to be coupled with something close to B, while one transistor has an open connection. Your "NOT sel" seems to do nothing apart from connecting plus and minus via a transistor.

It would help if you separate the different components better, and mark them in the sketch of the transistor/resistor layout.

Do you mean something like this?

I noticed I still had some goofs in copying my diagram from my notebook. Hopefully no more missing connections.

 

[Svein]

Just a hint: The simplest classic AND-gate looks something like this (attached file).

 

[Avencherus]

Just a hint: The simplest classic AND-gate looks something like this (attached file).

Diodes would be better for this? I'm actually a bit perplexed by how that even works. XD

I'm assuming I'm wrong, but looking at it my impression is that VCC would just always flow out, and the diodes would block A and B. What's the trick behind it?

 

[mfb]

Do you mean something like this?

I noticed I still had some goofs in copying my diagram from my notebook. Hopefully no more missing connections.

That looks fine.

The diode "AND" doesn't work in larger circuits (requires large currents at the input and doesn't deliver large currents at the output), you'll need the transistors for them.

 

[meBigGuy]

You best bet is to study CMOS logic since that is common.

Here are three basic 2:1 muxes (in 2 diagrams)

Fig 1 represent two different designs. AND/OR and NAND/NOR. The NAND/NOR uses less transistors in a CMOS implementation.

Fig 2 is a transmission gate based design at the transistor level.

It is important that you understand the logic of all three designs, and how PMOS and NMOS CMOS transistors work when used in logic circuits.

For example, the CMOS design for a NAND2 is: (from http://www.ibiblio.org/kuphaldt/electricCircuits/Digital/DIGI_3.html#xtocid110545)

Basically, when both A and B are High, both Q3 and Q4 (NMOS) are ON and Q1 and Q2 (PMOS) are off, so the output is low. Work through all the combinations of A and B until it feels intuitive. There is no shortcut. You just need to slog through it until it seems obvious.

If you want to design with other transistor logic families, they are all described on the page I referenced above. But, I advise sticking with CMOS since that is the basis of most all complex digital systems design.Your next challange, Understanding a master/slave D flop at the transistor level is going to open a new can of worms. Google "CMOS D flop" and look at images.
(discrete latches vs feedback latches)

My advice would be to very quickly jump forward to understanding how to put logic gates together to produce useful functions.

The only guys doing transistor level designs are standard cell library designers, and analog designers (like power supplies and amplifiers and IO interfaces).
Very few digital designers need to work at the transistor level. (but, it certainly helps for the designer to understand the internal structure, so don't skip that).

 

[Svein]

Diodes would be better for this? I'm actually a bit perplexed by how that even works. XD

Well, it works good enough for it to have been delivered in millions:

Observe that the diodes do the logic stuff, the transistors amplify and invert.

 

[Avencherus]

You best bet is to study CMOS logic since that is common.

Here are three basic 2:1 muxes (in 2 diagrams)

Fig 1 represent two different designs. AND/OR and NAND/NOR. The NAND/NOR uses less transistors in a CMOS implementation.

Fig 2 is a transmission gate based design at the transistor level.

It is important that you understand the logic of all three designs, and how PMOS and NMOS CMOS transistors work when used in logic circuits.

For example, the CMOS design for a NAND2 is: (from http://www.ibiblio.org/kuphaldt/electricCircuits/Digital/DIGI_3.html#xtocid110545)

Basically, when both A and B are High, both Q3 and Q4 (NMOS) are ON and Q1 and Q2 (PMOS) are off, so the output is low. Work through all the combinations of A and B until it feels intuitive. There is no shortcut. You just need to slog through it until it seems obvious.

If you want to design with other transistor logic families, they are all described on the page I referenced above. But, I advise sticking with CMOS since that is the basis of most all complex digital systems design.Your next challange, Understanding a master/slave D flop at the transistor level is going to open a new can of worms. Google "CMOS D flop" and look at images.
(discrete latches vs feedback latches)

My advice would be to very quickly jump forward to understanding how to put logic gates together to produce useful functions.

The only guys doing transistor level designs are standard cell library designers, and analog designers (like power supplies and amplifiers and IO interfaces).
Very few digital designers need to work at the transistor level. (but, it certainly helps for the designer to understand the internal structure, so don't skip that).

Oh my thanks so much for the resources. I will be ordering these next. I was mainly working with what I had from a kit, not to build anything serious, but I want to prove to myself that I can build these things and make them work in some way. Once I'm comfortable with them, I will just buy the ICs and begin building the next bigger thing. I just want to play around with each layer of abstraction. Possibly even take a tour of history on the way.

My next stop is building an oscillator with a flip flop, then start building all the various kinds of latches. I'm fairly comfortable with the schematics using general symbols, but when it comes to sitting face to face with a bread board it is indeed a can of worms. XD

 

[Avencherus]

Well, it works good enough for it to have been delivered in millions:
View attachment 90069Observe that the diodes do the logic stuff, the transistors amplify and invert.

I think I'm reading the diodes wrong. Am I imagining it, or do they get drawn facing differing directions at times? Look at the ones on the grounding look like they're shunting off the ground flow, but I know that wouldn't have much point. Is current flowing away from the arrow or towards it?

 

[Avencherus]

Well I did finally solve this thing. I had to modify the NOT segment by adding another transistor. I also ditched the extra transistors for the ANDs and OR, since I don't really need to control the voltage leaving the output in my crude little design. X)

 

[meBigGuy]

D3 and D4 do all the logic. If either input A or B is grounded the result is that Q1 is turned off through D3 or D4 which will cause the output to go high.
D1 and D2 merely protect against the input going below ground.

Current flows from positive to negative in the direction of the arrows in the bipolar transistors and the diodes.

The little squiggles indicate schottky diodes and transistors (The LS in LS00 indicates the low power schottky logic family, one of many).

You can review the various logic families here http://www.ti.com/lit/sg/sdyu001aa/sdyu001aa.pdf and every one has a different low level design.

 

[Avencherus]

D3 and D4 do all the logic. If either input A or B is grounded the result is that Q1 is turned off through D3 or D4 which will cause the output to go high.
D1 and D2 merely protect against the input going below ground.

Current flows from positive to negative in the direction of the arrows in the bipolar transistors and the diodes.

The little squiggles indicate schottky diodes and transistors (The LS in LS00 indicates the low power schottky logic family, one of many).

You can review the various logic families here http://www.ti.com/lit/sg/sdyu001aa/sdyu001aa.pdf and every one has a different low level design.

Thanks I will investigate further. I am very curious. I'm still kind of baffled by the ground connection. If it's blocked by a diode why even make the connection?

Some of the diagram is a bit beyond my current ability. I'm not too sure either about how electricity behaves down so many paths with all those resistor values.

 

[meBigGuy]

The diodes to ground in the TTL LS00 example are protection diodes to stop the input from undershooting to a negative voltage and causing substrate problems within the IC. They are pretty advanced, and you should ignore them. In fact, most of that circuit is pretty advanced other than understanding what D3 and D4 do to Q1.

Let's go back to the AND DTL circuit in post 6 where two diodes are connected to a resistor.
Let's assume perfect diodes that conduct current in the direction of the diode arrows, and do not conduct current in the other direction.
Let's also assume A and B can either be VCC ( a logic 1) or 0V (a logic 0), nothing in between.
Ground is not shown, but everything is measured with respect to ground.

The idea is that only when both inputs A and B are at VCC, will the output will be at VCC.
If A goes to 0, then it will pull the output to 0 also.
B is still at VCC when A is at 0, but its diode blocks it from boosting the output above 0V.
So this can happen: A=0 B=VCC OUT=VCC

If B goes to zero (and A is VCC) then the same thing happens.

If you now look at D3 and D4 in the TTL LS00 example, they work the same way to affect the turnon of Q1.

 

[Avencherus]

The diodes to ground in the TTL LS00 example are protection diodes to stop the input from undershooting to a negative voltage and causing substrate problems within the IC. They are pretty advanced, and you should ignore them. In fact, most of that circuit is pretty advanced other than understanding what D3 and D4 do to Q1.

Let's go back to the AND DTL circuit in post 6 where two diodes are connected to a resistor.
Let's assume perfect diodes that conduct current in the direction of the diode arrows, and do not conduct current in the other direction.
Let's also assume A and B can either be VCC ( a logic 1) or 0V (a logic 0), nothing in between.
Ground is not shown, but everything is measured with respect to ground.

The idea is that only when both inputs A and B are at VCC, will the output will be at VCC.
If A goes to 0, then it will pull the output to 0 also.
B is still at VCC when A is at 0, but its diode blocks it from boosting the output above 0V.
So this can happen: A=0 B=VCC OUT=VCC

If B goes to zero (and A is VCC) then the same thing happens.

If you now look at D3 and D4 in the TTL LS00 example, they work the same way to affect the turnon of Q1.

So is it that a voltage in A prevents the flow from the VCC entering and passing through the diode at A? Making it then flow to B, and if B is inactive it flows in there and gets grounded. But if B also has a voltage pushing against the diode it gets blocked there as well and passes on to the output path. Is that how is goes?

 

[meBigGuy]

Well, kind of. It can be said a bit simpler than that. There is no "then". Everything happens in parallel. You can think about it sequentially, but there is no sequence in reality.

Assume A and B are floating. VCC is provided to the output through the 10K resistor.

Now, connect VCC to A and B. It has no effect on the output since the diodes are off. No current flows through the diodes

Now connect A to 0. Current flows through A's diode pulling the output to ground. B's diode does not conduct since it can only conduct in the direction of its arrow.

if you connect B to 0 instead of A, then the current would flow through B's arrow.

If you connect them both to ground its hard to say which one the current will flow through. Since everything is ideal in this example, we can just say half through each diode.
In the real world there are diode voltage drops (~0.7V for silicon) and wire resistances that will determine how much of the current each leg will conduct.

In summary, either node A or B can pull the output to 0 through its diode. So the output is VCC only if A and B are VCC, hence the AND function.

 

[Avencherus]

Well, kind of. It can be said a bit simpler than that. There is no "then". Everything happens in parallel. You can think about it sequentially, but there is no sequence in reality.

Assume A and B are floating. VCC is provided to the output through the 10K resistor.

Now, connect VCC to A and B. It has no effect on the output since the diodes are off. No current flows through the diodes

Now connect A to 0. Current flows through A's diode pulling the output to ground. B's diode does not conduct since it can only conduct in the direction of its arrow.

if you connect B to 0 instead of A, then the current would flow through B's arrow.

If you connect them both to ground its hard to say which one the current will flow through. Since everything is ideal in this example, we can just say half through each diode.
In the real world there are diode voltage drops (~0.7V for silicon) and wire resistances that will determine how much of the current each leg will conduct.

In summary, either node A or B can pull the output to 0 through its diode. So the output is VCC only if A and B are VCC, hence the AND function.

Interesting. I think I'm learning more about diode behavior. I will have to experiment with it. Thanks for the information.