Pumped and source synchronous transmission

[dfx008]

Hi,

Basically I'm doing a report on a logic analyser lab - I realize this isn't the homework section - and I'm looking to extend a basic discussion on synchronous/asynchronous data transmission to analysis of pumped and source-synchronous transmission:

http://electronicdesign.com/Articles/Index.cfm?ArticleID=2974&pg=1

This seems to be quite a new field with not much theory out there and googling mostly reveals patent abstracts. Any further information/sources particularly on the theory would be extremely helpful. Thanks very much.

 

[berkeman]

Wow, what a terrible article from Electronic Design (that's not your fault; welcome to the PF!). 10x more words than necessary to present a technical concept, plus a commercial to start off the link (click in the upper right to skip the commercial).

You have to wonder about articles with so little technical meat, and grammatical errors like this:

Not only are they faster, but they're chang-ing how a system clocks data.

Outsourcing articles, maybe.

But beyond the obnoxious nature of the article, there may be some concepts that would be good for us to discuss. dfx008, could you please do us all a favor, and summarize the important technical points of the article? I'm especially interested in what they mean by double-pumped clocks...

Thanks, and welcome again to the PF.

 

[dfx008]

Thanks for the prompt reply.

I've found the original article from Tek which it seems was pretty much ripped off word for word from some sections along with the diagrams:

http://www.tek.com/Measurement/App_Notes/57_16987/eng/57W_16987_0.pdf

So far I've focused on the various different types of clocking innovations (double and quad pumped and source-synchronous clocking). This is on the SUT side.

What I'm slightly confused about is 2X and 4X clocking. Is this on the logic analyser side or is it yet another clocking innovation? And is the description that it is where 2 or more acquisition channels pool their resources to perform more effectively correct? And lastly, assuming that is correct, is there a simple correlation between analysing double/quad pumped architectures and 2X/4X clocking on the logic analyser side? Lots of questions, I appreciate! Thanks very much.