Sample & Hold in SPICE not holding charge using real elements

In summary: I'll try that. It looks like the capacitor is shorting to ground though.It's really easy to understand. I attached the spice file on the first post.
  • #1
40
0
Hi guys,

I'm having problem in HSPICE. I designed a Sample & Hold circuit using MOSFET switches (transmission gate). The problem is that when I activate the MOSFET switches, the capacitor doesn't hold the charge as expected (I did the simulation using ideal components, and the charge holds just fine).

I'm using PTM 130nm transistor models.

The simulation results are:
Ideal switches:
http://imageshack.us/photo/my-images/834/38cg.png/

MOS switches:

http://imageshack.us/photo/my-images/407/m385.png/

A drew the schematic to help the understanding of the circuit, and attached the spice file in this post.
http://imageshack.us/photo/my-images/801/uyg6.png/

Did anyone here have a problem like this one? My main purpose is to design a data converter, but I won't get the correct answer if I lose 300mV in this process.
What do you guys think?

Thank you in advance.
 

Attachments

  • sh.txt
    1 KB · Views: 429
Engineering news on Phys.org
  • #3
Lanot said:
Hi guys,

I'm having problem in HSPICE. I designed a Sample & Hold circuit using MOSFET switches (transmission gate). The problem is that when I activate the MOSFET switches, the capacitor doesn't hold the charge as expected (I did the simulation using ideal components, and the charge holds just fine).

I'm using PTM 130nm transistor models.

The simulation results are:
Ideal switches:
http://imageshack.us/photo/my-images/834/38cg.png/

MOS switches:

http://imageshack.us/photo/my-images/407/m385.png/

A drew the schematic to help the understanding of the circuit, and attached the spice file in this post.
http://imageshack.us/photo/my-images/801/uyg6.png/

Did anyone here have a problem like this one? My main purpose is to design a data converter, but I won't get the correct answer if I lose 300mV in this process.
What do you guys think?

Thank you in advance.

Why are you sampling in series? In a data converter the sampling capacitor is typically shunt relative to the input source. Look at the first slide in the pdf file UltrafastPED put up.
 
  • #4
analogdesign said:
Why are you sampling in series? In a data converter the sampling capacitor is typically shunt relative to the input source. Look at the first slide in the pdf file UltrafastPED put up.

That's because I'm planning to design a charge redistribution ADC, like SAR for example.
 
  • #5
Lanot said:
That's because I'm planning to design a charge redistribution ADC, like SAR for example.

OK. It could be lots of stuff. 12.8 pF is a pretty beefy sampling cap so you'll need a big switch to drive it. How did you dimension your sampling switch? What order are you activating the switches. As UltrafastPFD said, what are your time constants? Have you tried running really slow?

You could be getting charge injection because when you turn off the sampling switch you have a capacitive voltage divider.
 
  • #6
analogdesign said:
OK. It could be lots of stuff. 12.8 pF is a pretty beefy sampling cap so you'll need a big switch to drive it. How did you dimension your sampling switch? What order are you activating the switches. As UltrafastPFD said, what are your time constants? Have you tried running really slow?

You could be getting charge injection because when you turn off the sampling switch you have a capacitive voltage divider.

The same effect happens if a replace the 12.8pF to 12.8nF or to 12.8fF. What dimensions do you recommend? I'm using the NMOS W/L ratio as 10/1 and PMOS 20/1, both using the minimum channel length.
 
  • #7
Could you post a simulation of all your signals, including clock signals for the NMOS and PMOS switches?
 
  • #8
analogdesign said:
Could you post a simulation of all your signals, including clock signals for the NMOS and PMOS switches?

Of course:

http://img842.imageshack.us/img842/6696/477m.png [Broken]
 
Last edited by a moderator:
  • #9
Thanks. I can't really understand which signals are which, but it bugs me that the voltage across the capacitor doesn't track the input. When the top plate of the capacitor is connected to the signal, the bottom plate should be grounded. You must have a misconnection if that is what you are trying to do.
 
  • #10
analogdesign said:
Thanks. I can't really understand which signals are which, but it bugs me that the voltage across the capacitor doesn't track the input. When the top plate of the capacitor is connected to the signal, the bottom plate should be grounded. You must have a misconnection if that is what you are trying to do.

It's really easy to understand. I attached the spice file on the first post.
s7 and sa are the control signals for the nmos from the first two TG, s7n and san are the control signals for the pmos. sb is the control signal for the TG from the lower plate of the capacitor.
I use the model from: http://ptm.asu.edu/modelcard/130nm_bulk.txt (just renamed it)
Thank you.
 
  • #11
Hey Lanot,

I think I figured out your issue. I hadn't looked at the SPICE deck prior. You're referring the sampled signal to ground when you should refer it to the reference voltage. The voltage at the bottom plate of the capacitor during hold mode is V(pre) - V(in). In your schematic you precharge that node to ground, so the desired output voltage is -vin. Your switch models are probably not operating correctly if you are trying to have a node at -1 volt!

What you can do is sample with respect to the reference. So charge the bottom plate of the cap to Vref=1.2V. In that case, you will have the output voltage is Vref-Vin = 1.2-1 = 0.2 which is in range.

I think the confusion is between true ground and small signal ground.

Good luck!
 
  • Like
Likes 1 person
  • #12
analogdesign said:
Hey Lanot,

You're referring the sampled signal to ground when you should refer it to the reference voltage. The voltage at the bottom plate of the capacitor during hold mode is V(pre) - V(in). In your schematic you precharge that node to ground, so the desired output voltage is -vin. Your switch models are probably not operating correctly if you are trying to have a node at -1 volt!

What you can do is sample with respect to the reference. So charge the bottom plate of the cap to Vref=1.2V. In that case, you will have the output voltage is Vref-Vin = 1.2-1 = 0.2 which is in range.

I think the confusion is between true ground and small signal ground.

Good luck!

Sorry, I don't think I understand completely your answer yet. I tested the switches, and I think they are correct, it charges and discharges a capacitor just fine. I think that charging the bottom plate with an additional source isn't a good idea, since I will need that value from Vin to perform a charge redistribution with the additional capacitors later.
 
  • #13
Lanot,

The issue is your signal is below ground, and since you have 1.2 and 0 volt supplies that's not going to work. The signal is defined as the voltage across the cap. If you refer it to Vref then it moves in the right direction.

How is your comparator going to work if the input signal is below ground?
 
  • Like
Likes 1 person
  • #14
analogdesign said:
Lanot,

The issue is your signal is below ground, and since you have 1.2 and 0 volt supplies that's not going to work. The signal is defined as the voltage across the cap. If you refer it to Vref then it moves in the right direction.

How is your comparator going to work if the input signal is below ground?

I need this voltage to be negative to add it to the voltage across the equivalent capacitance on the next step of conversion (redistribution), like the way it's described in this document: http://www.ti.com/lit/an/slyt176/slyt176.pdf
 
  • #15
You need it to be negative compared to the small-signal ground, but you have it negative compared to true ground. If you want to set up your SAR like this you will have to run it off split rails. (positive and negative supplies).
 
  • Like
Likes 1 person
  • #16
analogdesign said:
You need it to be negative compared to the small-signal ground, but you have it negative compared to true ground. If you want to set up your SAR like this you will have to run it off split rails. (positive and negative supplies).

Hi analogdesign,
Thank you for your help.
I've designed a circuit with a differential input, but the positive output still give me the same error. The negative output is fine though. (look at the picture attached)

I've tried using an NMOS switch too, but it doesn't give me better results.

What do you think?
 

Attachments

  • sh.txt
    799 bytes · Views: 387
  • output_diff.png
    output_diff.png
    1.2 KB · Views: 597
  • #17
Lanot said:
Hi analogdesign,
Thank you for your help.
I've designed a circuit with a differential input, but the positive output still give me the same error. The negative output is fine though. (look at the picture attached)

I've tried using an NMOS switch too, but it doesn't give me better results.

What do you think?

Can you post a detailed schematic for me? I'll have a look.
 
  • #19
Hi Lanot,

The spice deck is for a single-ended version of your circuit. I suspect you are making a conceptual error with differential signal processing and I wanted to see the schematic to confirm.

The structure in slide 3 of that file is totally standard for bottom-plate sampling. I use it myself in every sampling circuit I design. Here is what I think you are doing wrong:

In a differential system, obviously the variable of interest is the difference between the two outputs (e.g, vod = vop - von).

In your simulation, comp_inn is going negative relative to ground. This a no-no. Both signals must remain between the rails (unless you REALLY know what you're doing.

So, set your common-mode somewhere like mid scale. Then the positive input is higher than that, and the negative input is nominally lower. The differential input can be bipolar (positive or negative).

For example. Your VDD=1.2V. So, set Vcm = 0.6 V. If you want a 1Vpp-diff signal, let vip range from 0.6V up to 0.85V or down to 0.35 V. Let vin range from 0.6 V down to 0.35 V and up to 0. 85 V. So, you will constrain both comp_in and comp_inn to between 0.85 V and 0.35 V. The signal will be between (0.85 - 0.35) and (0.35 - 0.85) or 0.5 - (-0.5) = 1 V. So you'll have 1 V differential swing.

Bottom line, keep all your signals between the rails. You're almost there. While I can't see the actual circuit you're simulating I think the issue is with your input range, not your circuit.
 
  • Like
Likes 1 person
  • #20
Hi,

I'm actually not familiar with differential designs.

I added a dc source before ground, and got the results attached. Is that correct?

I'm worried that the charge redistribution scheme won't work with these output levels, though.
 

Attachments

  • ckt.PNG
    ckt.PNG
    2.3 KB · Views: 595
  • output_diff2.png
    output_diff2.png
    1.6 KB · Views: 579
  • #21
That does look correct now! The vast majority of integrated circuits use differential signal processing internally. If you're interested in learning more here is a nice, gentle introduction. The charge distribution scheme ABSOLUTELY will work with those output levels. All that matters is the charge on the capacitors, which is given by the voltage across them. The absolute levels don't affect the capacitors, just the switches and the active devices you'll need to implement the comparator.

This will help you understand: http://www.ti.com/lit/an/sloa054d/sloa054d.pdf [Broken]
 
Last edited by a moderator:
  • Like
Likes 1 person
  • #22
Thank you very much, analogdesign!

Now I will proceed to the remaining of my design, and study this new approach.

Thanks again.
 
  • #23
analogdesign said:
Hi Lanot,
For example. Your VDD=1.2V. So, set Vcm = 0.6 V. If you want a 1Vpp-diff signal, let vip range from 0.6V up to 0.85V or down to 0.35 V. Let vin range from 0.6 V down to 0.35 V and up to 0. 85 V. So, you will constrain both comp_in and comp_inn to between 0.85 V and 0.35 V. The signal will be between (0.85 - 0.35) and (0.35 - 0.85) or 0.5 - (-0.5) = 1 V. So you'll have 1 V differential swing.

analogdesign,

I have one more question.

When you said that vip will range from 0.6V up to 0.85V, what do you mean? my "Vrefp" would be 0.85V and my vip would be 0.6V? or my vip would be 0.35V?

Thank you again.
 

What is sample and hold in SPICE?

Sample and hold is a component in SPICE (Simulation Program with Integrated Circuit Emphasis) that holds a voltage or current value for a specific amount of time before sampling and updating that value with a new one.

Why is the sample and hold in SPICE not holding charge using real elements?

This could be due to the presence of parasitic elements, such as stray capacitances and resistances, which can affect the performance of the sample and hold circuit. These elements can cause the charge to leak or dissipate, resulting in the sample and hold not holding the charge.

How can I improve the performance of sample and hold in SPICE?

To improve the performance of sample and hold in SPICE, you can use ideal elements instead of real ones, as ideal elements do not have parasitic effects. Additionally, you can add a buffer amplifier or use a higher precision sample and hold circuit.

Are there any limitations to using sample and hold in SPICE?

Yes, there are some limitations to using sample and hold in SPICE. One limitation is that it cannot hold a charge indefinitely, as there will always be some leakage or dissipation. Another limitation is that it may not accurately hold the voltage or current value for a long period of time due to the effects of parasitic elements.

What are some applications of sample and hold in SPICE?

Sample and hold in SPICE is commonly used in analog-to-digital converters (ADCs) to sample and hold an analog signal before converting it to a digital value. It is also used in communication systems to hold a signal for a specific amount of time before transmitting it. Additionally, it can be used in data acquisition systems to capture and hold sensor readings for processing.

Suggested for: Sample & Hold in SPICE not holding charge using real elements

Replies
8
Views
567
Replies
2
Views
740
Replies
6
Views
779
Replies
2
Views
888
Replies
3
Views
225
Replies
13
Views
1K
Replies
1
Views
1K
Replies
2
Views
703
Back
Top