Hi guys, I'm having problem in HSPICE. I designed a Sample & Hold circuit using MOSFET switches (transmission gate). The problem is that when I activate the MOSFET switches, the capacitor doesn't hold the charge as expected (I did the simulation using ideal components, and the charge holds just fine). I'm using PTM 130nm transistor models. The simulation results are: Ideal switches: http://imageshack.us/photo/my-images/834/38cg.png/ MOS switches: http://imageshack.us/photo/my-images/407/m385.png/ A drew the schematic to help the understanding of the circuit, and attached the spice file in this post. http://imageshack.us/photo/my-images/801/uyg6.png/ Did anyone here have a problem like this one? My main purpose is to design a data converter, but I won't get the correct answer if I lose 300mV in this process. What do you guys think? Thank you in advance.