Sequential vs combinational adder

[fysloc]

Homework Statement

Write the VHDL code for an n-bit sequential adder and an n-bit combinational adder using a full adder and observe the FPGA for each implementation.

Homework Equations

None

The Attempt at a Solution

My issue isn't the coding itself or anything of that sort (which is the purpose of the homework), just understanding what's the difference between a sequential adder and a combinational adder as it was not stated in the homework nor in any textbooks/class notes. My guess is that my original idea of an N-bit adder being N full adders placed together where the carryout is passed into the carryin of the next full adder would count as one of the designs, but am not sure what it would be called. Infact, the design I mentioned has been discussed in class but the prof never stated which design it was. Now being asked to do both designs, I tried to use google search to find out what's the difference, and sofar with no luck as the terms are very generic and I am not getting relevant search results. Again, the point of the homework is not to figure out what's the difference, just build them differently to see how the hardware changes in FPGA.

 

[Quinzio]

In my opinion, a sequencial adder may be something that you feed data into with a shift register.
A combinatorial adder is a fixed length adder, made of multiple stages.

But I'm just guessing here.