Simple Diode and Capacitor question

[FrogPad]

I'm trying to follow an example in the book that leads into more complicated circuits.

Consider a voltage source connected in series to first an ideal diode, and the diode is then connected (in series) to a capacitor. Let the input v_I be a sinusoid with a peak value V_p, and assume the diode to be ideal. As v_I goes positive, the diode conducts and the capacitor is charged so that v_O = v_I. (where v_O is the voltage measured across the capacitor). This situation continues until v_I reaches its peak value V_p. Beyond the peak, as v_I decreases the diode becomes reverse biased, and the output voltage remains constant at the value V_p.

I don't understand this: Beyond the peak, as v_I decreases the diode becomes reverse biased

I thought that an ideal diode has the characteristic, that when i_D >0 then the voltage across the diode is 0. So why is it that when the sinusoid is decreasing (it's still above zero right?) the diode is reverse biased?

Thanks in advance!

 

[FrogPad]

OH YEAH!

CIVIL

in a C(capacitor) the I(current) leads the V(voltage). So when the voltage is falling, I<0.

Never really used that until now. I guess there was a reason to learn it :)

 

[Ouabache]

So the capacitor is charging such that vo = vi. When the time-varying voltage is falling from its peak positive potential, don't forget the voltage at the cap. Can you intuitively appreciate why the diode becomes reverse biased after the peak?

 

[FrogPad]

Can you intuitively appreciate why the diode becomes reverse biased after the peak?

If I could sum up what this book is trying to accomplish, it would be that.

Honestly, no. I don't have an intuitive feeling why the diode becomes reverse biased. I understand the simple example I explained, but that was a precursor to explaining a voltage multiplier. I'm looking at the multiplier and am just lost. I mean I could perform circuit analysis, and really figure it out... but I need to gain that intuitive feeling. I have lab in a few hours, so I'm hoping the TA will help me understand it.

I have another question to follow. Let's say I have a voltage source that is in parallel with a three diode and capacitor (in series combinations). Thus, the voltage across D1+C1 is that same as that of D2+C2, and D3+C3. So when the current splits at the top node and crosses the capacitors it becomes out of phase with the voltage right? So, is I1, I2, and I3 in phase with each other? Should be right since:

I_S = C_1 \frac{dV_1}{dt} + C_2 \frac{dV_2}{dt} + C_3 \frac{dV_3}{dt}

So could we then conclude that phase changes (when dealing with capacitors) occur only when the current splits (I hope you know what I mean, I didn't write this thought that well)?

 

[SGT]

A diode is reverse biased when the voltage at the anode is lower than at the cathode, even if both are positive.

In your example, the capacitor is charged at V_p, so when v_i &lt; V_p the diode is reverse biased and no current flows.

 

[Ouabache]

Yes, SGT has caught my meaning.. the two voltages on either side of the diode are positive, but the cathode (side that is connected to the capacitor) is at a higher potential (peak of the cycle), while the anode is at lower positive potential (as the voltage decreases after peak). So yes it is reversed biased.

I don't know that much about voltage multipliers but if you do a search, there are some good references

 

[SGT]

If I could sum up what this book is trying to accomplish, it would be that.

Honestly, no. I don't have an intuitive feeling why the diode becomes reverse biased. I understand the simple example I explained, but that was a precursor to explaining a voltage multiplier. I'm looking at the multiplier and am just lost. I mean I could perform circuit analysis, and really figure it out... but I need to gain that intuitive feeling. I have lab in a few hours, so I'm hoping the TA will help me understand it.

I have another question to follow. Let's say I have a voltage source that is in parallel with a three diode and capacitor (in series combinations). Thus, the voltage across D1+C1 is that same as that of D2+C2, and D3+C3. So when the current splits at the top node and crosses the capacitors it becomes out of phase with the voltage right? So, is I1, I2, and I3 in phase with each other? Should be right since:

I_S = C_1 \frac{dV_1}{dt} + C_2 \frac{dV_2}{dt} + C_3 \frac{dV_3}{dt}

So could we then conclude that phase changes (when dealing with capacitors) occur only when the current splits (I hope you know what I mean, I didn't write this thought that well)?

No, if the capacitors are in parallel with the source they have the same phase. Only a combination resistor-capacitor or inductor-capacitor will cause a phase shift in the capacitor.
Of course, if you consider the small forward resistance of the diodes (a few ohms for a power diode) there will be a small phase shift at the capacitors, but this is of no importance at all.
By the way, in a voltage multiplyer the pairs diode-capacitor are not in parallel with the source.

 

[FrogPad]

Thank you both!

I think I have better understanding of these circuit combintions now. I talked with the TA for awhile and addressed my questions, he was very helpful in getting me to understand this stuff.