Strange impedance curve in LTSpice

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SUMMARY

The forum discussion focuses on analyzing the impedance curve of a non-ideal tantalum capacitor using LTSpice. The user observed an unexpected maximum in the impedance curve at approximately 100MHz, along with a phase polarity switch, which did not appear in their Octave simulation. The discrepancy arises because the LTSpice model includes parasitic inductance and a non-zero parallel capacitance by default, while the Octave simulation assumes an ideal capacitor. Disabling the parallel capacitance in LTSpice resolves the issue, aligning the results more closely with the expected behavior.

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hadoque
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Hi
I'm looking at an impedance curve of a non-ideal tantalum capacitor in LTSpice. The test circuit and impedance curve is seen in this screengrab:
http://www.apspektakel.com/bilder/tantal.png"
The spice file is here http://www.apspektakel.com/bilder/tantal.asc".
So, the imdpedance curve shows the expected impedance minimum, but also an unexpected maximum at about 100MHz, where there is also a polarity switch in phase. This feature does not show up if I do an impedance plot in octave:

Code:
octave:1> f = [1000:1000:1e9];
octave:2> C = 2e-3
C =  0.0020000
octave:3> R = 2e-3
R =  0.0020000
octave:4> L = 1e-9
L =  1.0000e-09
octave:5> z = R + f.*2*pi*j*L-1./(f.*2*pi*j*C)
octave:6> loglog(f,abs(z))
octave:7> semilogx(f,atand(imag(z)./real(z)))
Which result in these plots
http://www.apspektakel.com/bilder/tantal.svg"
http://www.apspektakel.com/bilder/phase.svg"

The parameters in the octave code are the same as in LTSpice component. Anyone know where this comes from? The phases look pretty different, is there something wrong with the test circuit?
 
Last edited by a moderator:
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You may want to look at the LTSpice model more closely. That looks like a typical parasitic resonance curve. If the model has a parasitic inductance built into it to model non-idealities, it would look just like that. The Octave simulation is an ideal capacitor so you don't see it.
 
Since I posted I've found out just that. The spice models has a non-zero parallel capacitance as default. It's disabled by setting the parallel capacitance to zero.
 

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