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Two port network model and analysis

  • #1

Homework Statement


Greetings. I am having difficulty with a couple of parts to a homework problem. Mainly coming up with the transfer functions to plot V_o. See the picture for the problem statement:
[PLAIN]http://img827.imageshack.us/img827/5481/problempa.jpg [Broken]


Homework Equations



[tex]l \leqq v_{ph}*T_{rise} / 10[/tex]

[tex] Z_o = Z_c = 75\Omega [/tex]

I've also included the model parameters for the two-port network:
[PLAIN]http://img8.imageshack.us/img8/1712/modelsz.jpg [Broken]

The Attempt at a Solution



I found T_rise to be 6.66ns. I am able to calculate L and C for the line using the characteristic impedance equation from Z so L = 0.5*10^-6 H/m and C = 88.88*10^-12 F/m. I'm having difficulty with the transfer functions. I can find it for the 7 model:

[tex]\frac{1/LC}{s^2+s\frac{R}{L}+\frac{1}{LC}} = H(s) [/tex]

But not for the other two. Also. In order to plot Vo correctly, we have to incorporate a delay operator with the ramp function as such:

[tex]\frac{1-e^{sT_{rise}/0.8}}{T_{rise}/0.8} = D(s) [/tex]

So our final plot would be the step response (or ramp, as my colleagues and I think the professor wants) of D(s)*H(s).

Any and all help would be greatly appreciated! Other examples for this type of problem is very difficult to find on the internet.
 
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Answers and Replies

  • #2
rude man
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I don't know about your various models, but it should be helpful to know the following: if an ideal transmission line is source-terminated in its characteristic impedance and the other end is open-circuited, there is no distortion of Vi at Vo. There is only a time-delay.

You can show this easily by using ABCD parameters for the resistor and for the line, then concatenating.
 
  • #3
I don't know about your various models, but it should be helpful to know the following: if an ideal transmission line is source-terminated in its characteristic impedance and the other end is open-circuited, there is no distortion of Vi at Vo. There is only a time-delay.

You can show this easily by using ABCD parameters for the resistor and for the line, then concatenating.
I think that's what the problem is. We have to show that measured delay in the line with the given parameters.
 
  • #4
rude man
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I am addressing only your parts 4 and 5. The 2nd and 3rd are standard lumped-parameter exercises. Not sure about the first. I would have said there is no finite rise time that will repoduce exactly at the output with a lumped-parameter circuit.

The delay time is simply physical line length divided by phase velocity = 0.1/1.5e8 s.
.
 
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