How to Choose TVS Diodes for ESD Protection?

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Discussion Overview

The discussion revolves around selecting TVS diodes for ESD protection in a cable continuity tester circuit. Participants explore the requirements for ESD protection, the voltage tolerances of components, and the implications of circuit design choices on ESD vulnerability.

Discussion Character

  • Technical explanation
  • Debate/contested
  • Exploratory

Main Points Raised

  • One participant expresses confusion about ESD protection and seeks advice on choosing TVS diodes, noting that their CPLD can be damaged by voltages exceeding 4V.
  • Another participant requests more details about the output and input connections to provide better guidance.
  • A participant clarifies the connection setup, indicating that ESD protection is needed between the CPLD and the wire under test, with a maximum output voltage of 3.3V.
  • Concerns are raised about estimating the peak pulse current and the voltage that may develop due to ESD, with a request for guidance on these calculations.
  • One participant suggests that for a 3.3V system, selecting a TVS diode with a standoff voltage of 3.3V or 4V is sufficient, emphasizing the importance of considering the capacitance of the TVS diode to avoid slowing down the circuit.
  • A participant shares their implementation of TVS diodes on the input side of their project but questions the necessity of protection on the output side, arguing that the TVS diode would discharge any static buildup quickly.
  • Another participant acknowledges that while the output is less sensitive than the input, additional protection could be beneficial for double failure protection.

Areas of Agreement / Disagreement

Participants express differing views on the necessity of ESD protection for the output side of the circuit, with some advocating for it while others believe it is unnecessary. The discussion remains unresolved regarding the best approach to ESD protection in this context.

Contextual Notes

Participants mention the need to consider circuit impedance and the potential impact of TVS diode capacitance on circuit performance, but these aspects remain unresolved.

saad87
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I'm developing a basic cable continuity tester. Essentially, the circuit drives a test vector onto the cable and reads back the output vector. The output has MOSFETs for buffers/drivers but the input is connected directly to the ICs (CPLD, in my case).

My concern is ESD. Unfortunately, I have very little experience in this area and am seeking advice on how to protect my devices from ESD. One thing I saw while browsing was TVS Diodes. Reading the literature on these only confused me more. I'm not sure what the highest voltage will develop that I need protection against. I do know my CPLD will be damaged if the the IO pins see more than 4V, so that's the voltage I can tolerate. Other than that, I'm a bit confused and seeking help here.

Any advice on choosing a TVS diode or, heck, another device for ESD Protection?

NOTE: I am aware that a continuity tester may not be enough and I should be measuring resistances. We have a separate machine for that so we're not bothering with including that in this machine.
 
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You need to give more info what is the output and what input you are driving to choose.
 
OK, the cable connects to a MOSFET's drain and the other connects to a CPLD's pins. The output high voltage is just 3.3V. To illustrate:

CPLD A's Output -> MOSFET -> Connector -> Wire Under Test -> Connector -> CPLD B's Input

I think there should be ESD protection between CPLD B and the wire.

Is this what you required? The cable's length can be upto 10 meters. Frequency of operation is just 62.5kHz.
 
Last edited:
After some reading, it seems I need determine the peak pulse current. But how do I estimate the voltage that will develop due to ESD? I believe I need to divide that by the impedence of the circuit. Would appreciate any pointers regarding this.
 
saad87 said:
After some reading, it seems I need determine the peak pulse current. But how do I estimate the voltage that will develop due to ESD? I believe I need to divide that by the impedence of the circuit. Would appreciate any pointers regarding this.

You don't need to calculate anything. If your input is only 3.3v get the 3.3v or 4v TVS.

Here is the link to Digikey:

http://search.digikey.com/scripts/DkSearch/dksus.dll

type in TVS, then choose standoff voltage to 3.3v and you have plenty.

TVS has nothing to do with your circuit, all you need to know is you are running 3.3v logic so you find a TVS that has standoff of 3.3v and you are done. The thing you need to be careful is the capacitance of the TVS, you don't want to get a high wattage one and the result is it has so much capacitance that it slow down your circuit. I used a lot of these and I use the smaller SOT package, a dual up and down in one package and I never have problem with it even running at processor speed.

Good luck.
 
Thank you very much, yungman!
 
I had a small question about ESD.

I have implemented TVS diodes on my project at the input side. However, the output is still unprotected. It's a bit like this:

CPLD 1 -> Logic-Level MOSFET -> WIRE UNDER TEST -> TVS DIODE -> Pull up -> CPLD 2.

So the input side is protected from ESD. But the output is still left bare. However, I think they are not needed because if there is a static build up somewhere on the wire, it will be discharged quickly by the TVS diode as it's the quickest path to ground. So it doesn't matter if the output is left unprotected, the TVS diode protects both.

Am I correct in my understanding? Would appreciate some advice.
 
Output is nowhere as sensitive as the input. But if you really want to, you can do it too. I think the CE require this for double failure protection or something. Been a long time.
 

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