Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

Understanding Instruction Cycle?

  1. Dec 17, 2014 #1
    A basic instruction cycle consists of these 5 stages.

    1. IF - Instruction Fetch
    2. RD - Instruction Decode and Register Read
    3. EX - Execute
    4. MA - Memory Access
    5. WB - Write Back

    I understood the meaning of all the stages accept 4th MA (Memory access), whats the significance of this stage.
     
  2. jcsd
  3. Dec 17, 2014 #2

    rcgldr

    User Avatar
    Homework Helper

    Step 4 Memory access - implies memory reads, since step 5 includes write back, which I assume means write back to memory.

    Step 2 - register read - this doesn't always happen, at least not at step 2. Take the case of an add immediate to memory / subtract immediate from memory / compare immediate with memory. The memory read needs to occur before the add / subtract / compare can occur.
     
  4. Dec 17, 2014 #3

    phinds

    User Avatar
    Gold Member
    2016 Award

    steps 4 and 5 also do not always happen. If, for example, you perform an operation that just changes a register or moves one register's value to another register or stuff like that, there is no need for any memory access beyond the instruction fetch.

    SO ... your statement really should say "A basic instruction cycle consists of these 5 POSSIBLE stages."
     
    Last edited: Dec 17, 2014
  5. Dec 17, 2014 #4

    FactChecker

    User Avatar
    Science Advisor
    Gold Member

    Everything starts in memory, even the program instructions. Your example is getting data that the program needs. As @phinds says, the memory access you are referring to may not be necessary for some instructions. Many instructions need to use some data that is stored in memory. When data from memory is needed, it can be quite involved. It may require moving data from the slowest level of memory, to an intermediate speed memory, to the fastest access memory. The processor may have looked ahead and began pulling the data in several cycles early so it would be immediately available in the fastest memory when this instruction is executed.
     
  6. Dec 19, 2014 #5
    Yeah Surely MA stage wouldn't do anything, if we have to operate operands from registers itself.
    Over Internet what I've found is this

    MA(Memory Access) does following operation

    • If load or store instruction, then access memory
    • If branch instruction, replace PC with destination address

    ##2^{nd}## point is clear, I'm confused with ##1^{st}## point.

    Suppose we have load and store instruction like this
    ##R_1 \leftarrow m[A_1##]
    ##m[A_2] \rightarrow R_2##
    ##R_3 \leftarrow m[A_3] + m[A_4]##
    what MA stage will do for the above instructions
     
  7. Dec 20, 2014 #6

    FactChecker

    User Avatar
    Science Advisor
    Gold Member

    I think you have the MA out of order. It should be before EX if it refers to getting the data that EX needs for its operation. Maybe the instruction set you are using does not exactly match up with the conceptual partitioning of your original post, but data must be brought from memory somewhere in your notation.
     
  8. Dec 20, 2014 #7

    phinds

    User Avatar
    Gold Member
    2016 Award

    I think I must be missing something in your question. You seem to be asking "when the instruction requires a memory fetch, what does the memory fetch do?" It fetches from memory.
     
  9. Dec 25, 2014 #8
    Actually The exam I'm preparing for, asks questions on pipe-lining on load and store architecture. So it is irrelevant to mention

    ##R_3 \leftarrow m[A_3] + m[A_4]##

    because a load/store architecture only allows memory to be accessed by load and store operations, and all values for an operation need to be loaded from memory and be present in registers. So a load/store architecture only allows operations like

    ##(I) R_1 \leftarrow m[A_1]##
    ##(II) m[A_2] \leftarrow R_2##
    ##(III) R_3 \leftarrow R_4 + R_5##

    Now, I've this following concept in my mind. Please suggest whether I'm right or wrong.

    1. For instruction (I) MA stage will fetch data from memory from a particular address and will write back into register ##R_1## at WB stage.
    2. For instruction (II) MA stage will store data of register ##R_2## into memory at specified address.
     
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook