Which Transistor Circuit Design is More Effective for Controlling a Nixie Clock?

[roeb]

I'm designing a circuit for a nixie clock and I seem to have two options for how I want to turn on the nixie.

http://img16.imageshack.us/img16/9181/circuit3l.th.jpg

The circuit on the left is what I originally prototyped and it seems to work fine; however, my friend has suggested that I try the circuit on the right. He claims that it's better because it puts the 'transistor' (not sure which one he is talking about) more into saturation. I'm really just trying to make something that drops 170 volts on the 18k resistor when 5 V is applied to the base of the NPN transistor. Are there any benefits to either design? It seems to me like they are basically doing the same thing. I should probably also add that eventually I plan on switching the nixie on/off at a rate of 30-60 Hz. Does anyone see anything wrong with this design?

Here's the code for the Falstad circuit simulator if you want to play with it.
$ 1 5.0E-6 10.20027730826997 50 5.0 50
R 112 288 80 288 0 0 40.0 5.0 0.0 0.0 0.5
r 112 288 160 288 0 10000.0
t 160 288 192 288 0 1 0.571991418107053 0.5767152473982993 100.0
t 256 208 272 208 0 -1 -0.5275036835365654 -0.6323984251546335 100.0
r 272 224 272 352 0 18000.0
w 192 304 192 352 0
w 192 352 272 352 0
g 272 352 272 384 0
r 192 272 192 208 0 1000000.0
r 192 208 192 160 0 1000000.0
w 256 208 192 208 0
R 272 144 272 96 0 0 40.0 170.0 0.0 0.0 0.5
w 192 160 272 160 0
w 272 160 272 144 0
w 272 192 272 160 0
R 416 288 384 288 0 0 40.0 0.0 0.0 0.0 0.5
t 480 288 496 288 0 1 -169.99999984950003 4.999999998019801E-10 100.0
r 416 288 480 288 0 10000.0
t 544 208 560 208 0 -1 169.99999979820004 -1.9999995970465534E-7 100.0
r 544 208 496 208 0 1000000.0
r 496 208 496 128 0 1000000.0
w 496 272 496 208 0
R 576 128 576 80 0 0 40.0 170.0 0.0 0.0 0.5
w 496 128 576 128 0
w 576 128 576 192 0
w 576 192 560 192 0
r 560 256 560 336 0 18000.0
w 496 304 496 336 0
w 496 336 560 336 0
g 560 336 560 384 0
w 560 256 560 224 0

 

[Bob S]

I think the first one is better, because there is a lower value resistor pullup on the pnp base when the npn is off. I would change the pnp base pullup resistor to perhaps 50 k (1/20th of the npn collector resistor).
Do you really want to pull the nixies up to 170 volts with a pnp open collector and a common-cathode nixie circuit, because using an open collector npn pulldown and a common-anode nixie circuit would be better.
[added] If you use a common-anode ckt, you need only one npn transistor with a 200 volt V_ceo rating. Are you using a bcd-to-decimal driver (74HC42) with active low?
Bob S

 

[roeb]

Thanks for the reply. I'm planning on using a microcontroller to act as the driver (it will switch on each digit in software), so it will basically be acting like an bcd to decimal driver. I may need to redesign, thanks for the info.

-roeb