Xilinx software to sketch AND and OR gates

  1. 1. The problem statement, all variables and given/known data
    In the Xilinx software symbol library (student edition version 10.1), the maximum number of inputs for AND and OR gates is 9. What would you do if a 10-input AND and OR gates are needed? Draw the schematic diagrams and show the connections.


    2. Relevant equations
    (a1+a2+....+a10)=(a1+a2+....+a9) +a10

    Boolean Equations:
    AND: multiply each input = output
    OR: add each input = output

    3. The attempt at a solution
    Put the AND operations to 9 AND input and then pass the output to the two inputs with another input as a10.

    Similar thing can be done to OR gates.


    I have attached my attempt sketch. It looks like I have 11 inputs in total and I need 10. How can I sketch the connections of the 10-input gates?
     

    Attached Files:

  2. jcsd
  3. Xilinx ISE has a notation for something we might call a "bus". It is a name follow by an interval specifier. See the example below.

    [​IMG]
     
  4. So you could label each dangling wire, and then connect all ten wires together to a bus named "a(9:0)" just as the bus "Avail(3:0)" picture above.
     
  5. I think I need to take two 5-input AND gates and connect the 10-inputs. Then take 1 2-input AND gate and connect output of two gates to the input of gate. Will the whole system function as a 10 input AND gate?

    How do I represent that? I've attached my attempt
     

    Attached Files:

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