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VHDL coding -- Design a component that uses a 4-to-1 multiplexer

  1. Mar 10, 2015 #1
    1. The problem statement, all variables and given/known data
    Design a component that uses a 4-to-1 multiplexer to choose between one
    of four different operations
    to get the result from. Each of the operations and the multiplexer
    should be behavioral design in their
    own modules / files to be used in the overall component design as
    separate components. The
    component being design must use structural design to provide the inputs
    to the components along with
    getting their results.
    The four operations expected are as follows:
    - AND -- when selection bits are 00
    - OR – when selection bits are 01
    - XOR – when selection bits are 10
    - NOT – when selection bits are 11
    Each module is responsible for only 1 operation, so there should be a
    total of five different modules /
    components including the multiplexer being used in the overall component
    design. Whenever a new
    operation is selected or new inputs are provided to change the output of
    the operations the multiplexer
    should determine its new output.
    Each of the operations can be assumed to only require two inputs, each 1
    bit, to do the operations
    except for the NOT operation, you can choose which input you want to
    invert the logic of. The overall
    component design should have two inputs, selections bits and an output.
    Every gate in the design
    should have a 3 ns delay, while NOT gates should have no delay.



    2. Relevant equations
    it seems as my logic is correct but modelsim wont run my code and i dont know how to integrate the 3ns delay into my code.

    3. The attempt at a solution
    library ieee;
    use ieee.std_logic_1164.all

    entity and is
    port(i1,i2: in std_logic;
    f1: out std_logic);
    end entity and;

    architecture and_beh of and is
    begin
    f1<= i1 and i2;
    end architecture and_beh;


    library ieee;
    use ieee.std_logic_1164.all

    entity or is
    port(i1,i2: in std_logic;
    f2: out std_logic);
    end entity or;

    architecture or_beh of or is
    begin
    f2<= i1 or i2;
    end architecture or_beh;

    library ieee;
    use ieee.std_logic_1164.all

    entity xor is
    port(i1,i2: in std_logic;
    f3: out std_logic);
    end entity xor;

    architecture xor_beh of xor is
    begin
    f3<= i1 xor i2;
    end architecture xor_beh;

    library ieee;
    use ieee.std_logic_1164.all

    entity not is
    port(i1: in std_logic;
    f4: out std_logic);
    end entity not;

    architecture not_beh of not is
    begin
    f4<= not i1;
    end architecture not_beh;


    library ieee;
    use ieee.std_logic_1164.all;

    entity strct is
    port(a,b: in std_logic;
    f: out std_logic);
    end entity strct;

    architecture strct_beh of strct is
    signal s1,s2,s3,s4: stf_logic;

    component and is
    port(i1,i2: in std_logic;
    f1: out std_logic);
    end component and;

    component or is
    port(i1,i2: in std_logic;
    f2: out std_logic);
    end component or;

    component xor is
    port(i1,i2: in std_logic;
    f3: out std_logic);
    end component xor;

    component not is
    port(i1: in std_logic;
    f4: out std_logic);
    end component not;

    begin
    M1: and port map(i1=>a,i2=>b,f1=>s1);
    M2: or port map(i1=>a,i2=>b,f2=>s2);
    M3: xor port map(i1=>a,i2=>b,f3=>s3);
    M4: not port map(i1=>a,f4=>s4);

    end architecture strct_beh;

    library ieee;
    use ieee.std_logic_1164.all

    entity mxer is
    port(s1,s2,s3,s4: in std_logic;
    sel: in std_logic_vector(1downto0);
    f5: out std_logic);
    end entity mxer;

    architecture mxer_beh of mxer is
    signal sel: std_logic;
    begin
    process(s1,s2,s3,s4,sel)
    begin
    if(sel="00")then
    f5<=s1;
    elsif(sel="01")then
    f5<=s2;
    elsif(sel="10")then
    f5<=s3;
    elsif(sel="11")then
    f5<=s4;
    end if;
    end process;
    end architecture mxer_beh;
     
  2. jcsd
  3. Mar 14, 2015 #2
    First of all whenever you design or want to make something in VHDL it is good practice to first make a diagram in which you show your modules within your top module. You can keep track of your idea and maybe foresee problems in the process. And when you want to explain your design when you have a problem, it is easier for someone to help when they can look at that diagram than read/listen to a story like you do here. Because now I really have to focus to understand your design in conjunction with your code to understand it.

    But for your problem: VHDL is primarily used by FPGA's. When you have a combinatorial design like you do here you think about logic gates that are connected and work one after another really quickly. While in reality your standard FPGA works synchronous on a clock. And thus your design should be synchronous/a-synchrounous too for the best results. The delay the gates have cause an instability or meta-instability. That all said I still wonder why this is a problem with such a small design.
     
  4. Mar 17, 2015 #3

    donpacino

    User Avatar
    Gold Member

    does this code have to be synthesizable?
    if not it is very easy to incorporate a delay into the code
    If it does, you will need a clock input to your devices

    http://www.ics.uci.edu/~jmoorkan/vhdlref/conc_s_a.html

    as for why it not running your code, many things could be wrong. why don't you try one entity at a time.

    In the future follow JHPMeer's advice about diagrams and using latex to organize your code
     
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