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Tracy_sysu
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Hello, everyone!Now I'm studying VHDL, and our teacher gave us some questions as follows:
1. Complete the following code fragment and try to synthesize the VHDL:
process begin
wait until Clk = '1';
Phase <= "0" after 0 ns; Phase <= "1" after 10 ns;
end process;
What is the error message? Synthesize this code, and explain the results:
process begin
wait until Clk_x_2 = '1';
case (Phase) is
when '0' => Phase <= '1'; when others => Phase <= '0';
end case;
end process;
2.Consider the following processes:
S1: process (clk) begin
if clk'EVENT and clk = '1' then count <= count + inc; end if;
end process;
S2: process (clk) begin
if rst = '1' then count <= 0;
elsif clk'EVENT and clk = '1' then count <= count + inc;
end if;
end process;
S3: process (clk, rst) begin
if rst = '1' then count <= 0; elsif clk'EVENT and clk = '1' then
count <= count + inc; sum <= count + sum;
end if;
end process;
S4: process (clk) begin
if clk'EVENT and clk = '1' then if rst = '1' then count <= 0;
else count <= count + inc; end if;
end if;
end process;
S5: process (clk, rst) begin
if rst = '1' then count <= 0;
elsif clk'EVENT and clk = '1' then count <= count + inc;
else count <= count + 1;
end if;
end process;
S6: process (clk, rst) begin
if rst = '1' then count <= 0;
elsif clk'EVENT and clk = '1' then count <= count + inc;
end if; inc <= not dec;
end process;
Write code to drive each of these processes and simulate them. Explain any errors or problems you encounter. Try to synthesize your code and check that the results behave correctly and match the simulation results. Explain any differences in behavior or any problems you encounter.
For these two questions, I have n o idea about them, is there anyone could help me?
1. Complete the following code fragment and try to synthesize the VHDL:
process begin
wait until Clk = '1';
Phase <= "0" after 0 ns; Phase <= "1" after 10 ns;
end process;
What is the error message? Synthesize this code, and explain the results:
process begin
wait until Clk_x_2 = '1';
case (Phase) is
when '0' => Phase <= '1'; when others => Phase <= '0';
end case;
end process;
2.Consider the following processes:
S1: process (clk) begin
if clk'EVENT and clk = '1' then count <= count + inc; end if;
end process;
S2: process (clk) begin
if rst = '1' then count <= 0;
elsif clk'EVENT and clk = '1' then count <= count + inc;
end if;
end process;
S3: process (clk, rst) begin
if rst = '1' then count <= 0; elsif clk'EVENT and clk = '1' then
count <= count + inc; sum <= count + sum;
end if;
end process;
S4: process (clk) begin
if clk'EVENT and clk = '1' then if rst = '1' then count <= 0;
else count <= count + inc; end if;
end if;
end process;
S5: process (clk, rst) begin
if rst = '1' then count <= 0;
elsif clk'EVENT and clk = '1' then count <= count + inc;
else count <= count + 1;
end if;
end process;
S6: process (clk, rst) begin
if rst = '1' then count <= 0;
elsif clk'EVENT and clk = '1' then count <= count + inc;
end if; inc <= not dec;
end process;
Write code to drive each of these processes and simulate them. Explain any errors or problems you encounter. Try to synthesize your code and check that the results behave correctly and match the simulation results. Explain any differences in behavior or any problems you encounter.
For these two questions, I have n o idea about them, is there anyone could help me?